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參數(shù)資料
| 型號(hào)： | TAPC640 |
| 廠商： | Lineage Power |
| 英文描述： | High-Speed Switching ATM Port Controller (APC)(高速開(kāi)關(guān)ATM端口控制器) |
| 中文描述： | 高速開(kāi)關(guān)ATM端口控制器（APC）（高速開(kāi)關(guān)自動(dòng)柜員機(jī)端口控制器） |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大小： | 165K |
| 代理商： | TAPC640 |
Product Brief
August 2000
TAPC640
High-Speed Switching ATM Port Controller (APC)
Introduction
The ATM port controller (APC) IC is part of the
Lucent high-speed switching chip set that provides a
highly integrated, innovative, and complete VLSI
solution for implementing the ATM layer functionality/
core of an ATM switch system. The chip set enables
construction of high-performance, feature rich, and
cost-effective asynchronous transfer mode (ATM)
switches, scalable over a wide range of switching
capacities.
Features
I
Provides a comprehensive single-chip solution for
implementing all ATM layer functions needed at an
ATM switch port.
I
Can be configured in a variety of switching modes
for flexible operation:
— Performs as an ATM switch port card by sup-
porting linear aggregation of up to 622 Mbits/s
of ATM traffic at the physical layer interface (full
duplex).
— Operates as a stand-alone, single-chip 32
×
32
shared memory switch or an N:1 concentrator
(622 Mbits/s total switching).
— Operates in conjunction with another APC as a
2
×
2 (1.2 Gbits/s total switching capacity) dual
APC-based switch (no separate external
switch fabric needed).
I
Performs ATM layer user network interface (UNI)
and network node interface (NNI) management
functions.
I
Provides two independently operating full-duplex
UTOPIA II compatible interfaces:
— Controls up to 31 full-duplex multiple physical
layer (MPHY) ports on the physical layer side.
— Allows either UTOPIA interface to operate as
16-bit or 8-bit data.
— Allows any MPHY to be configured as a UNI or
NNI.
I
Supports up to 64K connections with scalable
external memory:
— Manages virtual connection parameter table in
external memory.
— Optionally performs the ATM Forum compliant
dual leaky-bucket policing for up to 64K VCs.
— Facilitates call setup and tear down through
VC parameter table update via high-perfor-
mance microprocessor port.
— Optionally translates or passes the generic
flow control (GFC) field of the egress ATM cell
header for NNI or UNI applications.
— Performs virtual path identifier (VPI)/virtual
channel identifier (VCI) translation for up to
64K connections on egress while allowing
reusability of same VPI/VCI on different UNIs.
I
Maintains a variety of optional per-connection,
per-port, and per-device statistics counters in
external memory and on-chip.
I
Provides dual interfaces to high-speed switching
switch fabrics to facilitate construction of redundant
systems for fault tolerance.
I
Supports spatial and logical multicasting for up to
32 destination ports on egress (31 MPHY ports
and 1 microprocessor interface port).
I
Provides a generic 32-bit microprocessor interface
with interrupt.
I
Supports high-speed read and write direct memory
access (DMA) modes for cell extraction and inser-
tion via the microprocessor interface.
I
Provides input/output (bidirectional) queue man-
agement for an N
×
N switch fabric for over
100 Gbits/s capacity and up to 31 MPHY ports and
one microprocessor port:
— Queues up to 512K ATM cells in external mem-
ory, organized in a per-VC, fully-shared queue-
ing architecture.
— Supports five traffic classes via novel schedul-
ing algorithms, including a WFQ type sched-
uler to provide per-VC QoS assurance.
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