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參數資料
| 型號： | TB5T1LDW |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 外設及接口 |
| 英文描述： | Low Power 5V RS232 Dual Driver/Receiver with 0.1?μF Capacitors; Package: SO; No of Pins: 16; Temperature Range: -40?°C to 85?°C |
| 中文描述： | 電可擦除可編程邏輯器件 |
| 文件頁數： | 1/17頁 |
| 文件大小： | 437K |
| 代理商： | TB5T1LDW |
www.ti.com
FEATURES
Functional Replacement for the Agere BTF1A
Driver Features
– Third-State Logic Low Output
– ESD Protection HBM > 3 kV, CDM > 2 kV
– No Line Loading when Vcc = 0
– Capable of Driving 50-
loads
– 2.0-ns Maximum Propagation Delay
– 0.2-ns Output Skew (typical)
Receiver Features
– High-Input Impedance Approximately 8 k
– 4.0-ns Maximum Propagation Delay
– 50-mV Hysteresis
– Slew Rate Limited (1 ns min 80% to 20%)
– ESD Protection HBM > 3 kV, CDM > 2 kV
– -1.1-V to 7.1-V Input Voltage Range
Common Device Features
– Common Enable for Each Driver/Receiver
Pair
– Operating Temperature Range: -40
°
C to
85
°
C
– Single 5.0 V
±
10% Supply
– Available in Gull-Wing SOIC (JEDEC
MS-013, DW) and SOIC (D) Package
9
10
16
15
14
13
12
11
1
2
3
4
5
6
7
8
GND
V
CC
RO2
RO1
DI1
DI2
ED
ER
RI1
RI1
DO1
RI2
RI2
DO1
DO2
DO2
DW AND D PACKAGE
(TOP VIEW)
DESCRIPTION
The TB5T1 device is a dual differential driver/receiver
circuit that transmits and receives digital data over
balanced transmission lines. The dual drivers trans-
late input TTL logic levels to differential pseudo-ECL
output levels. The dual receivers convert differen-
tial-input logic levels to TTL output levels. Each driver
or receiver pair has its own common enable control
allowing serial data and a control clock to be
transmitted and received on a single integrated cir-
cuit. The TB5T1 requires the customer to supply
termination resistors on the circuit board.
DI1
DI2
ED
ER
RO2
RO1
RI1
RI1
RI2
RI2
DO1
DO1
DO2
DO2
ENABLE TRUTH TABLE
TB5T1
SLLS589B–NOVEMBER 2003–REVISED MAY 2004
DUAL DIFFERENTIAL PECL DRIVER/RECEIVER
In circuits with termination resistors, the line remains
impedance- matched when the circuit is powered
down. The driver does not load the line when it is
powered down.
All devices are characterized for operation from -40
°
C
to 85
°
C.
The logic inputs of this device include internal pull-up
resistors of approximately 40 k
that are connected
to V
to ensure a logical high level input if the inputs
are open circuited.
PIN ASSIGNMENTS
FUNCTIONAL BLOCK DIAGRAM
ED
0
1
0
1
ER
0
0
1
1
D1
D2
R1
R2
Active
Disabled
Active
Disabled
Active
Disabled
Active
Disabled
Active
Active
Disabled
Disabled
Active
Active
Disabled
Disabled
The power-down loading characteristics of the re-
ceiver input circuit are approximately 8 k
relative to
the power supplies; hence, it does not load the
transmission line when the circuit is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 2003–2004, Texas Instruments Incorporated
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