
TOSHIBA
TOSHIBA CORPORATION
1/4
TC74AC Series
TC74AC390
The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equip-
ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
Features:
High Speed:
f
MAX
= 160MHz (typ.) at V
CC
= 5V
Low Power Dissipation:
I
CC
= 8
μ
A (max.) at T
a
= 25
°
C
High Noise Immunity:
V
NIH
= V
NIL
= 28% V
CC
(min.)
Symmetrical Output Impedance:
S
I
OH
S
= I
OL
= 24mA
(min.). Capability of driving 50
transmission lines.
Balanced Propagation Delays:
t
pLH
= t
pHL
Wide Operating Voltage Range:
V
CC
(opr.) = 2V~5.5V
Pin and Function Compatible with 74HC390
Available in 16-pin DIP and 150 mil SOIC
Pin Assignment
Block Diagram
The TC74AC390 is an advanced high speed CMOS DUAL
DECADE COUNTER fabricated with silicon gate and double-
layer metal wiring C
2
MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL, while maintaining the CMOS low
power dissipation.
It consists of two independent 4-bit counters, each com-
posed of a divide-by-two and a divide-by-five counter. The
divide-by-two counter is incremented on the negative going
transition of clock A (CKA). The divide-by-five counter is
incremented on the negative going transition of clock B
(CKB). The counter can be cascaded to form decade, bi-qui-
nary, or various combinations up to a divide-by-100 counter.
When the CLEAR input is set high, the Q outputs are set to
low independent of the clock inputs.
All inputs are equipped with protection circuits against
static discharge or transient excess voltage.
Truth Table
X:
Don’t Care
IEC Logic Symbol
1
2
3
4
5
6
7
16
15
14
13
12
11
10
V
CC
2CKA
2CLR
2Q
A
2CKB
2Q
B
2Q
C
1CKA
1CLR
1Q
A
1CKB
1Q
B
1Q
C
1Q
D
9
2Q
D
8
GND
(TOP VIEW)
CKA
CLR
CKB
1,15
2,14
4,12
BINARY
COUNTER
QUINARY
COUNTER
V
CC
=16, GND=8
3,13
QA
5,11
6,10
7,9
QB
QC
QD
INPUTS
OUTPUTS
CKA
CKB
CLR
QA
QB
QC
QD
X
X
H
L
L
L
L
X
L
BINARY COUNT UP
X
L
QUINARY COUNT UP
(2)
(1)
(4)
1CLR
1CKA
1CKB
CTR
CT=0
DIV2
DIV5
(3)
(5)
(6)
(7)
1QA
1QB
1QC
1QD
0
+
+
2
CT
(14)
(15)
(12)
2CLR
2CKA
2CKB
CTR
CT=0
DIV2
DIV5
(13)
(11)
(10)
(9)
2QA
2QB
2QC
2QD
0
+
+
2
CT