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參數資料
| 型號： | TCN75-5.0MUAG |
| 廠商： | Microchip Technology |
| 文件頁數： | 8/20頁 |
| 文件大小： | 567K |
| 描述： | IC TEMP SENSOR SRL 5.0V 8MSOP |
| 標準包裝： | 100 |
| 功能： | 溫度監控系統（傳感器） |
| 傳感器類型： | 內部 |
| 感應溫度： | -55°C ~ 125°C |
| 精確度： | ±3°C（最小值） |
| 拓撲： | ADC（三角積分型），寄存器庫 |
| 輸出類型： | 2 線串行 |
| 輸出警報： | 是 |
| 輸出風扇： | 無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-MSOP |
| 包裝： | 管件 |
TCN75
DS21490C-page 8
?2006 Microchip Technology Inc.
4.0
SHUTDOWN MODE
When the appropriate bit is set in the configuration reg-
ister (CONFIG) the TCN75 enters its low-power Shut-
down mode (I
DD
= 1 糀, typical) and the temperature-
to-digital conversion process is halted. The TCN75s
bus interface remains active and TEMP, T
SET
, and
T
HYST
may be read from and written to. Transitions on
SDA or SCL due to external bus activity may increase
the standby power consumption. If the TCN75 is in
Interrupt mode, the state of INT/CMPTR will be reset
upon entering Shutdown mode.
4.1
Fault Queue
To lessen the probability of spurious activation of INT/
CMPTR the TCN75 may be programmed to filter out
transient events. This is done by programming the
desired value into the Fault Queue. Logic inside the
TCN75 will prevent the device from triggering INT/
CMPTR unless the programmed number of sequential
temperature-to-digital conversions yield the same
qualitative result. In other words, the value reported in
TEMP must remain above T
SET
or below T
HYST
for the
consecutive number of cycles programmed in the Fault
Queue. Up to a six-cycle filter may be selected. See
Section 5.0 Register Set and Programmers
ModeL , Register Set and Programmers Model.
4.2
Serial Port Operation
The Serial Clock input (SCL) and bidirectional data port
(SDA) form a 2-wire bidirectional serial port for pro-
gramming and interrogating the TCN75. The following
table indicates TCN75 conventions that are used in this
bus scheme.
TABLE 4-1:
SERIAL BUS CONVENTIONS
All transfers take place under control of a host, usually
a CPU or microcontroller, acting as the Master, which
provides the clock signal for all transfers. The TCN75
always operates as a Slave. This serial protocol is
illustrated in Figure 5-1. All data transfers have two
phases; and all bytes are transferred MSB first.
Accesses are initiated by a Start condition, followed by
a device address byte and one or more data bytes. The
device address byte includes a Read/Write selection
bit. Each access must be terminated by a Stop condi-
tion. A convention called Acknowledge (ACK) confirms
receipt of each byte. Note that SDA can change only
during periods when SCL is LOW (SDA changes while
SCL is HIGH are reserved for Start and Stop condi-
tions).
4.3
Start Condition (Start)
The TCN75 continuously monitors the SDA and SCL
lines for a Start condition (a HIGH-to-LOW transition of
SDA while SCL is HIGH), and will not respond until this
condition is met.
Term
Explanation
Transmitter The device sending data to the bus.
Receiver The device receiving data from the bus.
Master
The device which controls the bus: initiating
transfers (Start), generating the clock, and
terminating transfers (Stop).
Slave
The device addressed by the master.
Start
A unique condition signaling the beginning of
a transfer indicated by SDA falling (High
Low) while SCL is high.
Stop
A unique condition signaling the end of a
transfer indicated by SDA rising (Low High)
while SCL is high.
ACK
A Receiver acknowledges the receipt of each
byte with this unique condition. The Receiver
drives SDA low during SCL high of the ACK
clock-pulse. The Master provides the clock
pulse for the ACK cycle.
NOT Busy When the bus is idle, both SDA & SCL will
remain high.
Data Valid The state of SDA must remain stable during
the High period of SCL in order for a data bit
to be considered valid. SDA only changes
state while SCL is low during normal data
transfers. (See Start and Stop conditions).
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