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參數(shù)資料
| 型號： | TCS59SM704AFT-75 |
| 廠商： | Toshiba Corporation |
| 英文描述： | 8M×4Banks×4Bits Synchronous DRAM(4組8M×4位同步動態(tài)RAM) |
| 中文描述： | 8米× 4Banks × 4Bits同步DRAM（4組8米× 4位同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 1/49頁 |
| 文件大小： | 2421K |
| 代理商： | TCS59SM704AFT-75 |
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TC59SM716/08/04AFT/AFTL-70,-75,-80
2000-02-08 1/49
TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in
general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of
the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure
of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please
ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications.
Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
The products described in this document are subject to the foreign exchange and foreign trade laws.
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
The information contained herein is subject to change without notice.
980910EBA1
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
2,097,152-WORDS
×
4
BANKS
×
16-BITS SYNCHRONOUS DYNAMIC RAM
4,194,304-WORDS
×
4
BANKS
×
8-BITS SYNCHRONOUS DYNAMIC RAM
8,388,608-WORDS
×
4
BANKS
×
4-BITS SYNCHRONOUS DYNAMIC RAM
DESCRIPTION
TC59SM716AFT/AFTL is a CMOS synchronous dynamic random access memory organized as 2,097,152-words
×
4 banks
×
16 bits and TC59SM708AFT/AFTL is organized as 4,194,304 words
×
4 banks
×
8 bits and
TC59SM704AFT/AFTL is organized as 8,388,608 words
×
4 banks
×
4 bits. Fully synchronous operations are
referenced to the positive edges of clock input and can transfer data up to 143M words per second. These devices
are controlled by commands setting. Each bank are kept active so that DRAM core sense amplifiers can be used as
a cache. The refresh functions, either Auto Refresh or Self Refresh are easy to use. By having a programmable
Mode Register, the system can choose the most suitable modes which will maximize its performance. These devices
are ideal for main memory in applications such as work-stations.
FEATURES
TC59SM716/M708/M704
PARAMETER
-70
-75
-80
t
CK
Clock Cycle Time (min)
7 ns
7.5 ns
8 ns
t
RAS
Active to
Precharge Command Period (min)
42 ns
45 ns
48 ns
t
AC
Access Time from CLK (max)
5.4 ns
5.4 ns
6 ns
t
RC
Ref/Active to Ref/Active Command Period (min)
57 ns
65 ns
68 ns
I
CC1
Operation Current (max) (Single bank)
80 mA
75 mA
70 mA
I
CC4
Burst Operation Current (max)
100 mA
95 mA
90 mA
I
CC6
Self-Refresh Current (max)
2 mA
2 mA
2 mA
Single power supply of 3.3 V
±
0.3 V
Up to 143 MHz clock frequency
Synchronous operations: All signals referenced to the positive edges of clock
Architecture:
Pipeline
Organization
TC59SM716AFT/AFTL: 2,097,152 words
×
4 banks
×
16 bits
TC59SM708AFT/AFTL: 4,194,304 words
×
4 banks
×
8 bits
TC59SM704AFT/AFTL: 8,388,608 words
×
4 banks
×
4 bits
Programmable Mode register
Auto Refresh and Self Refresh
Burst Length:
1, 2, 4, 8, Full page
CAS Latency:
2, 3
Single Write Mode
Burst Stop Function
Byte Data Controlled by L-DQM, U-DQM (TC59SM716)
4K Refresh cycles/64 ms
Interface:
LVTTL
Package
TC59SM716AFT/AFTL: TSOPII54-P-400-0.80B
TC59SM708AFT/AFTL: TSOPII54-P-400-0.80B
TC59SM704AFT/AFTL: TSOPII54-P-400-0.80B
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