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參數(shù)資料
型號(hào): TEA1750T/N1,518
廠商: NXP Semiconductors
文件頁(yè)數(shù): 10/29頁(yè)
文件大小: 163K
描述: IC PFC CONTROLLER DCM16SOIC
標(biāo)準(zhǔn)包裝: 2,500
系列: GreenChip™ III
模式: 間歇導(dǎo)電(DCM)
頻率 - 開關(guān): 100kHz ~ 150kHz
電流 - 啟動(dòng): 60µA
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SO
包裝: 帶卷 (TR)
TEA1750_2
?NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02  15 December 2008
10 of 29
NXP Semiconductors
TEA1750
GreenChip III SMPS control IC
7.2.6   Burst mode control
When the output power of the yback converter (see
Section
7.3) is low, the yback
converter switches over to frequency reduction mode. When frequency reduction mode is
entered by the yback controller, the power factor correction circuit switches to burst mode
control.
In burst mode control, switching of the power factor correction circuit is inhibited until the
voltage on the VOSENSE pin has dropped to V
burst(L)
. Switching then restarts with a
soft-start to avoid audible noise (see
Section
7.2.5). As soon as the voltage on the
VOSENSE pin reaches V
burst(H)
 the soft-stop circuit is activated, again to avoid audible
noise. During the soft-stop time the output voltage of the power factor correction circuit
overshoots, depending on the soft-start resistor and capacitor, R
SS1
 and C
SS1,
 on the
PFCSENSE pin. As the V
burst(H)
 voltage is well below the V
reg(VOSENSE)
 voltage, the PFC
output voltage does not reach the normal operation output voltage of the power factor
correction circuit in a typical application due to this overshoot.
The burst mode repetition rate is dened by the output power and the value of the bus
capacitor, C
bus
.
During burst mode operation the PFCCOMP pin is clamped between a voltage of
2.7 V (typ) and 3.9 V (typ). The lower clamp voltage limits the maximum power that is
delivered during burst mode operation and yields a more sinusoidal input current during
the burst pulse. The upper clamp voltage ensures that the PFC can return to its normal
regulation point in a limited amount of time when returning from burst mode.
As soon as the yback converter leaves frequency reduction mode, the power factor
correction circuit restores normal operation. To prevent continuous on and off switching of
the PFC circuit, a small hysteresis is built in (50 mV (typ) on the FBCTRL pin).
Fig 5.    Soft start-up and soft stop of PFC
SOFT START
SOFT STOP
CONTROL
OCP
+
11
PFCSENSE
0.5 V
I
start(soft)PFC d 60 礎(chǔ)
S1
R
SS1
C
SS1
R
SENSE1
014aaa018
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