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參數資料
| 型號： | TFP201CPZP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, POWER, THERMALLY ENHANCED, PLASTIC, TQFP-100 |
| 文件頁數： | 4/22頁 |
| 文件大小： | 286K |
| 代理商： | TFP201CPZP |
TFP201, TFP201A
TI PanelBus
DIGITAL RECEIVER
SLDS116 - MARCH 2000
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
TFP201/201A clocking and data synchronization
The TFP201/201A receives a clock reference from the TMDS transmitter that has a period equal to the pixel
time, Tpix. The frequency of this clock is also referred to as the pixel rate. Since the TMDS encoded data on
Rx[2:0] contains 10 bits per 8 bit pixel it follows that the Rx[2:0] serial bit rate is 10 times the pixel rate. For
example, the required pixel rate to support an SXGA resolution with 60 Hz refresh rate is 165 MHz. The TMDS
serial bit rate is 10x the pixel rate or 1.65 Gb/s. Due to the transmission of this high-speed digital bit stream, on
three separate channels (or twisted-pair wires) of long distances (3-5 meters), phase synchronization between
the data steams and the input reference clock is not guaranteed. In addition, skew between the three data
channels is common. The TFP201/201A uses a 4x oversampling scheme of the input data streams to achieve
reliable synchronization with up to 1-Tpix channel-to-channel skew tolerance. Accumulated jitter on the clock
and data lines due to reflections and external noise sources is also typical of high speed serial data transmission,
hence the TFP201/201A’s design for high jitter tolerance.
The input clock to the TFP201/201A is conditioned by a phase-locked-loop (PLL) to remove high frequency jitter
from the clock. The PLL provides four 10x clock outputs of different phase to locate and sync the TMDS data
streams (4x oversampling). During active display the pixel data is encoded to be transitioned minimized,
whereas in blank, the control data is encoded to be transition maximized. (See TMDS encodings in
Appendix
A) A DVI compliant transmitter is required to transmit in blank for a minimum period of time, 128-Tpix, to ensure
sufficient time for data synchronization when the receiver sees a transition maximized code. Synchronization
during blank, when the data is transition maximized, ensures reliable data bit boundary detection. Phase
synchronization to the data streams is unique for each of the three input channels and is maintained as long
as the link remains active.
TFP201/201A TMDS input levels and input impedance matching
The TMDS inputs to the TFP201/201A receiver have single-ended termination to AVDD of value Rt. The value
of Rt is determined by the external resistor value placed between EXT_RES and AVDD. The value of Rt must
be matched to the single-ended characteristic impedance, Zo, of the cable being used. The value of Rt is:
Rt = (1/10)(Resistor at EXT_RES to AVDD).
ADV
ANCE
INFORMA
TION
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TFP201PZP | 功能描述:顯示接口集成電路 PanelBus DVI Receiver 112MHz RoHS:否 制造商:Texas Instruments 電源電流:125 mA 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:WQFN-60 封裝:Reel |
| TFP201PZPG4 | 功能描述:顯示接口集成電路 PanelBus DVI Rcvr RoHS:否 制造商:Texas Instruments 電源電流:125 mA 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:WQFN-60 封裝:Reel |
| TFP2N60 | 制造商:TAK_CHEONG 制造商全稱:Tak Cheong Electronics (Holdings) Co.,Ltd 功能描述:N-Channel Power MOSFET 2.0A, 600V, 4.6Ω |
| TFP2N60A | 制造商:TAK_CHEONG 制造商全稱:Tak Cheong Electronics (Holdings) Co.,Ltd 功能描述:N-Channel Power MOSFET 2.1A, 600V, 5.6Ω |
| TFP2N65 | 制造商:TAK_CHEONG 制造商全稱:Tak Cheong Electronics (Holdings) Co.,Ltd 功能描述:N-Channel Power MOSFET 1.9A, 650V, 7.5?? |
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