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參數(shù)資料
| 型號(hào)： | TFP401CPZP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, POWER, THERMALLY ENHANCED, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 18/22頁 |
| 文件大小： | 285K |
| 代理商： | TFP401CPZP |
TFP401, TFP401A
TI PanelBus
DIGITAL RECEIVER
SLDS120 - MARCH 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
PIXS
4
DI
Pixel select – Selects between one or two pixels per clock output modes. During the 2-pixel/clock mode, both
even pixels, QE[23:0], and odd pixels, QO[23:0], are output in tandem on a given clock cycle. During
1-pixel/clock, even and odd pixels are output sequentially, one at a time, with the even pixel first, on the even
pixel bus, QE[23:0]. (The first pixel per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the
odd pixel.)
High : 2-pixel/clock
Low: 1-pixel/clock
PVDD
97
VDD
PLL VDD – Power supply for internal PLL
QE[0:7]
10-17
DO
Even blue pixel output – Output for even and odd blue pixels when in 1-pixel/clock mode. Output for even only
blue pixel when in 2-pixel per clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE0/pin 10
MSB: QE7/pin 17
QE[8:15]
20-27
DO
Even green pixel output – Output for even and odd green pixels when in 1-pixel/clock mode. Output for even
only green pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE8/pin 20
MSB: QE15/pin 27
QE[16:23]
30-37
DO
Even red pixel output – Output for even and odd red pixels when in 1-pixel/clock mode. Output for even only
red pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE16/pin 30
MSB: QE23/pin 37
QO[0:7]
49-56
DO
Odd blue pixel output – Output for odd only blue pixel when in 2-pixel/clock mode. Not used, and held low,
when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO0/pin 49
MSB: QO7/pin 56
QO[8:15]
59-66
DO
Odd green pixel output – Output for odd only green pixel when in 2-pixel/clock mode. Not used, and held low,
when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO8/pin 59
MSB: QO15/pin 66
QO[16:23]
69-75,77
DO
Odd red pixel output – Output for odd only red pixel when in 2-pixel/clock mode. Not used, and held low, when
in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO16/pin 69
MSB: QO23/pin 77
RxC+
93
AI
Clock positive receiver input – Positive side of reference clock. TMDS low voltage signal differential input pair
RxC-
94
AI
Clock negative receiver input – Negative side of reference clock. TMDS low voltage signal differential input
pair.
Rx0+
90
AI
Channel-0 positive receiver input – Positive side of channel-0. TMDS low voltage signal differential input pair.
Channel-0 receives blue pixel data in active display and HSYNC, VSYNC control signals in blank.
Rx0-
91
AI
Channel-0 negative receiver input – Negative side of channel-0. TMDS low voltage signal differential input
pair.
Rx1+
85
AI
Channel-1 positive receiver input – Positive side of channel-1 TMDS low voltage signal differential input pair.
Channel-1 receives green pixel data in active display and CTL1 control signals in blank.
Rx1-
86
AI
Channel-1 negative receiver input – Negative side of channel-1 TMDS low voltage signal differential input pair
Rx2+
80
AI
Channel-2 positive receiver input – Positive side of channel-2 TMDS low voltage signal differential input pair.
Channel-2 receives red pixel data in active display and CTL2, CTL3 control signals in blank.
ADV
ANCE
INFORMA
TION
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