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參數資料
| 型號： | TFP503PZP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PANELBUS HDCP DIGITAL RECEIVER |
| 中文描述： | PANELBUS支持HDCP數字接收機 |
| 文件頁數： | 1/27頁 |
| 文件大?。?/td> | 445K |
| 代理商： | TFP503PZP |
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SLDS149 AUGUST 2004
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Supports UXGA Resolution (Output Pixel
Rates up to 165 MHz)
Digital Visual Interface (DVI) and
High-Bandwidth Digital Content Protection
(HDCP) Specification Compliant
1
True-Color, 24 Bits/Pixel, 48-Bit Dual Pixel
Output Mode, 16.7M Colors at 1 or 2 Pixels
Per Clock
Laser-Trimmed (50-
) Input Stage for
Optimum Fixed Impedance Matching
Skew Tolerant up to One Pixel Clock Cycle
(High Clock and Data Jitter Tolerance)
4x Over-Sampling for Reduced Bit-Error
Rates and Better Performance Over Longer
Cables
Reduced Power Consumption From 1.8-V
Core Operation With 3.3-V I/Os and
Supplies
2
Reduced Ground Bounce Using
Time-Staggered Pixel Outputs
Lowest Noise and Best Power Dissipation
Using TI 100-Terminal TQFP PowerPAD
Packaging
Advanced Technology Using TI’s 0.18-
μ
m
EPIC-5
CMOS Process
Embedded Preprogrammed
High-Bandwidth Digital Content Protection
(HDCP) Keys
description
The TFP503 is a Texas Instruments
PanelBus
flat-panel display product, part of a comprehensive family of
end-to-end DVI 1.0-compliant solutions. Targeted primarily at desktop LCD monitors, DLP and LCD projectors,
and digital TVs, the TFP503 finds applications in any design requiring high-speed digital interface with the
additional benefit of an extremely robust and innovative encryption scheme for digital content protection.
The TFP503 supports display resolutions up to UXGA, including the standard HDTV formats, in 24-bit true color
pixel format. The TFP503 offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN
panels, and provides an option for time-staggered pixel outputs for reduced ground-bounce.
PowerPAD advanced packaging technology results in best-of-class power dissipation, footprint, and ultra-low
ground inductance.
The TFP503 combines
PanelBus
circuit innovation and unique implementation for HDCP key protection with
TI’s advanced 0.18-
μ
m EPIC-5 CMOS process technology to achieve a completely secure, reliable,
low-powered, low-noise, high-speed, digital interface solution.
The TFP503 comes with embedded preprogrammed HDCP keys, thus eliminating the need for an external
storage device to store the HDCP keys or the need for the customer to purchase HDCP keys from the licensing
authority. An encryption scheme ensures that the embedded HDCP keys are encrypted, thus providing highest
level of key security.
Footnotes:
1.
The digital visual interface (DVI) specification is an industry standard developed by the digital display working group (DDWG) for highspeed
digital connection to digital displays. The highbandwidth digital content protection system (HDCP) is an industry standard for protecting
DVI outputs from being copied. HDCP was developed by Intel Corporation and is licensed by the Digital Content Protection, LLC. The
TFP503 is compliant to the DVI Rev. 1.0 and HDCP Rev. 1.0 specifications.
The TFP503 has an internal voltage regulator that provides the 1.8 V core power supply from the externally supplied 3.3 V supplies.
2.
Copyright
2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PanelBus
, PowerPAD and EPIC-5 are trademarks of Texas Instruments.
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