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參數(shù)資料
型號(hào)： THS10082CDAR
廠商： TEXAS INSTRUMENTS INC
元件分類： ADC
英文描述： 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
封裝： GREEN, PLASTIC, TSSOP-32
文件頁(yè)數(shù)： 19/37頁(yè)
文件大小： 375K
代理商： THS10082CDAR
THS10082
SLAS254B MAY 2002 REVISED NOVEMBER 2002
www.ti.com
26
FIFO TRIGGER LEVEL
Bit 2 and bit 3 (TRIG1, TRIG0) of control register 1 are used to set the trigger level of the FIFO (see Table 13). If the trigger
level is reached, the DATA_AV (data available) signal becomes active according to the setting of the signal DATA_AV to
indicate to the processor that the ADC values can be read.
Table 13 shows four different programmable trigger levels for each configuration. The FIFO trigger level, which can be
selected, is dependent on the number of input channels. One channel is considered as two inputs in differential
configuration, or one single-ended input. The processor, therefore, always reads the data from the FIFO in the same order
and is able to distinguish between the channels.
Table 13. FIFO Trigger Level
BIT 3
TRIG1
BIT 2
TRIG0
TRIGGER LEVEL
FOR 1 CHANNEL
(ADC values)
TRIGGER LEVEL
FOR 2 CHANNELS
(ADC values)
0
01
02
0
1
04
1
0
08
1
14
12
TIMING AND SIGNAL DESCRIPTION OF THE THS10082
The reading from the THS10082 and writing to the THS10082 is performed by using the chip select inputs (CS0, CS1),
the write input WR and the read input RD. The write input is configurable to a combined read/write input (R/W). This is
desired in cases where the connected processor consists of a combined read/write output signal (R/W). The two chip select
inputs can be used to interface easily to a processor.
Reading from the THS10082 takes place by an internal RDint signal, which is generated from the logical combination of
the external signals CS0, CS1, and RD (see Figure 35). This signal is then used to strobe the words out of the FIFO and
to enable the output buffers. The last external signal (either CS0, CS1, or RD) to become valid makes RDint active while
the write input (WR) is inactive. The first of those external signals going to its inactive state then deactivates RDint.
Writing to the THS10082 takes place by an internal WRint signal, which is generated from the logical combination of the
external signals CS0, CS1 and WR. This signal is then used to strobe the control words into the control registers 0 and
1. The last external signal (either CS0, CS1, or WR) to become valid makes WRint active while the read input (RD) is
inactive. The first of those external signals going to its inactive state then deactivates WRint.
Read Enable
Write Enable
Control/Data
Registers
CS0
CS1
RD
WR
Data Bits
Figure 35. Logical Combination of CS0, CS1, RD, and WR
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
THS10082EVM 功能描述:EVALUATION MODULE FOR THS10082 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
THS10082IDA 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10 BIT High Speed AD RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
THS10082IDAG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10 Bit 8 MSPS Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
THS1009 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
THS1009CDA 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER
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