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參數資料
| 型號： | THS10082IDAR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| 封裝： | GREEN, PLASTIC, TSSOP-32 |
| 文件頁數： | 11/37頁 |
| 文件大?。?/td> | 350K |
| 代理商： | THS10082IDAR |
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THS10082
SLAS254B MAY 2002 REVISED NOVEMBER 2002
www.ti.com
19
FIFO DESCRIPTION
In order to facilitate an efficient connection to today’s processors, the THS10082 is supplied with a FIFO. This integrated
FIFO enables a problem-free processing of data with today’s processors. The FIFO is provided as a flexible circular buffer.
The circular buffer integrated in the THS10082 stores up to 16 conversion values. Therefore, the amount of interrupts to
be served by a processor can be reduced significantly.
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16
1
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7
Read Pointer
Trigger Pointer
Write Pointer
Data in FIFO
Free
Figure 29. Circular Buffer
The converted data of the THS10082 is automatically written into the FIFO. To control the writing and reading process, a
write pointer, a read pointer and a trigger pointer are used. The read pointer always shows the location which is read next.
The write pointer indicates the location which contains the last written sample. With a selection of multiple analog input
channels, the converted values are written in a predefined sequence to the circular buffer (autoscan mode). In this way,
the channel information for the reading processor is continually maintained.
The FIFO can be programmed through the control register of the ADC. The user has the ability to select a specific trigger
level according to Table 13 in order to choose the configuration which best fits the application. The FIFO provides the signal
DATA_AV, which signals the processor to read the amount of data equal to the trigger level selected in Table 13. The signal
DATA_AV becomes active when the trigger condition is satisfied. The trigger condition is satisfied when as many values
as selected for the trigger level are written into the FIFO.
The signal DATA_AV could be connected to an interrupt input of a processor. In every interrupt service routine call, the
processor must read the amount of data equal to the trigger level from the ADC. The first data represents the first channel
according to the autoscan mode, which is shown in Table 10. The channel information is, therefore, always maintained.
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| THS1009CDA | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| THS1009 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| THS1009CDA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| THS1009CDAG4 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| THS1009CDAR | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
| THS1009CDARG4 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER |
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