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參數資料
型號: THS1009CDA
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
封裝: PLASTIC, TSSOP-32
文件頁數: 17/31頁
文件大小: 289K
代理商: THS1009CDA
THS1009
SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002
www.ti.com
24
Read Timing (using R/W, CS0-controlled)
Figure 31 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write input
R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0
is the last external signal of CS0, CS1, and R/W which becomes valid. The reading of the data should be done with
a certain timing relative to the conversion clock CONV_CLK, as illustrated in Figure 31.
10%
90%
10%
tsu(CONV_CLKL–CSOL)
tsu(CSOH–CONV_CLKL)
tw(CS)
tsu(R/W)
th(R/W)
ta
th
CONV_CLK
CS0
CS1
R/W
RD
D(0–11)
Figure 31. Read Timing Diagram Using R/W (CS0-controlled)
Read Timing Parameter (CS0-controlled)
PARAMETER
MIN
TYP
MAX
UNIT
tsu(CONV_CLKL–CSOL)
Setup time, CONV_CLK low before CS valid
10
ns
tsu(CSOH–CONV_CLKL)
Setup time, CS invalid to CONV_CLK low
20
ns
tsu(R/W)
Setup time, R/W high to last CS valid
0
ns
ta
Access time, last CS valid to data valid
0
10
ns
th
Hold time, first CS invalid to data invalid
0
5
ns
th(R/W)
Hold time, first external CS invalid to R/W change
5
ns
tw(CS)
Pulse duration, CS active
10
ns
相關PDF資料
PDF描述
THS1009IDA 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
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相關代理商/技術參數
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