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參數資料
| 型號： | THS1030IPWR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, TSSOP-28 |
| 文件頁數： | 4/37頁 |
| 文件大小： | 727K |
| 代理商： | THS1030IPWR |
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THS1030
3V TO 5.5V, 10BIT, 30 MSPS
CMOS ANALOGTODIGITAL CONVERTER
SLAS243E NOVEMBER 1999 REVISED DECEMBER 2003
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
The analog input AIN is sampled in the sample and hold unit, the output of which feeds the ADC core, where
the process of analog to digital conversion is performed against ADC reference voltages, REFTF and REFBF.
Connecting the MODE pin to one of three voltages, AGND, AVDD or AVDD/2 sets up operating configurations.
The three settings open or close internal switches to select one of the three basic methods of ADC reference
generation.
Depending on the user’s choice of operating configuration, the ADC reference voltages may come from the
internal reference buffer or may be fed from completely external sources. Where the reference buffer is
employed, the user can choose to drive it from the onboard reference generator (ORG), or may use an external
voltage source. A specific configuration is selected by connections to the REFSENSE, VREF, REFTS and
REFBS, and REFTF and REFBF pins, along with any external voltage sources selected by the user.
The ADC core drives out through output buffers to the data pins D0 to D9. The output buffers can be disabled
by the OE pin.
A single, sample-rate clock (30 MHz maximum) is required at pin CLK. The analog input signal is sampled on
the rising edge of CLK, and corresponding data is output after following third rising edge.
The STBY pin controls the THS1030 power down.
The user-chosen operating configuration and reference voltages determine what input signal voltage range the
THS1030 can handle.
The following sections explain:
D The internal signal flow of the device, and how the input signal span is related to the ADC reference voltages
D The ways in which the ADC reference voltages can be buffered internally, or externally applied
D How to set the onboard reference generator output, if required, and several examples of complete
configurations
signal processing chain (sample and hold, ADC)
Figure 11 shows the signal flow through the sample and hold unit to the ADC core.
Sample
and
Hold
1
1/2
ADC
Core
VP+
VP
REFTF
REFBF
AIN
REFTS
REFBS
Figure 11. Analog Input Signal Flow
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相關代理商/技術參數 |
參數描述 |
|---|---|
| THS1030IPWRG4 | 功能描述:模數轉換器 - ADC 10-Bit 30 MSPS 1-Ch Pin Comp RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1030SOIC | 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.7 V . 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER |
| THS1030TSSOP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.7 V . 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER |
| THS1031 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.7 V . 5.5 V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER |
| THS1031CDW | 功能描述:模數轉換器 - ADC _ RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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