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參數資料
| 型號： | THS1041IDWR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, SOIC-28 |
| 文件頁數： | 17/41頁 |
| 文件大小： | 810K |
| 代理商： | THS1041IDWR |
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THS1041
SLAS289C OCTOBER 2001 REVISED OCTOBER 2004
24
www.ti.com
PRINCIPLES OF OPERATION
operating configuration examples (continued)
Figure 37 shows a configuration using external ADC references for digitizing a differential input with span 0.8 V.
To maximize the signal swing at the ADC core, the PGA gain is set to 2.5 to give a 2-Vp-p output from the PGA.
MODE is tied to ground to disable the internal reference buffer. The external ADC reference sources must set
REFT 1 V higher than REFB to set the ADC input span to 2 Vp-p, and the voltages provided by the external
sources must be centered near AVDD/2 for best ADC operation. REFSENSE is shown tied to AVDD to disable
the internal bandgap refence (A1), though other components in the system may use the VREF output if desired.
External ADC references are best suited to applications which require the tighter reference voltage tolerance
and temperature coefficient than the internal bandgap reference (A1) can provide, or where the references are
to be shared among several THS1041 ADCs for best matching of their ADC channels.
AIN+
AIN
REFB
MODE
REFSENSE
AVDD
1.7 V
1.3 V
1.7 V
1.3 V
1.5 V
REFT
2 V
1 V
0.1
F
10
F
20 pF
20
20
10
F
10
F
Figure 37. Operating Configuration: 0.8-V Differential Input and External ADC References
clamp operation
10-Bit
DAC
_
+
CLAMPIN
CLAMP
AIN+
RIN
CIN
V(Clamp)
Control Register (Bit CLINT)
S/H
VIN
SW1
CLAMPOUT
Figure 38. Schematic of Clamp Circuitry
The THS1041 provides a clamp function for restoring a dc reference level to the signal at AIN+ or AIN which
has been lost through ac-coupling from the signal source to this pin.
Figure 38 and Figure 39 show an example of using the clamp to restore the black level of a composite video
input ac-coupled to AIN+. While the clamp pin is held high, the clamp amplifier forces the voltage at AIN+ to equal
the clamp reference voltage, setting the dc voltage at AIN+ for the video black level.
After power up, the clamp reference voltage is the voltage on the CLAMPIN pin. This reference can instead be
taken from the internal CLAMP DAC by suitably programming the THS1041 clamp and control registers.
Clamp acquisition and clamp droop design calculations are discussed later.
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| THS1041IPWRG4 | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| THS1041CDWG4 | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| THS1041IDW | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| THS1041IDWRG4 | 功能描述:模數轉換器 - ADC 10 Bit 40 MSPS Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1041IPW | 功能描述:模數轉換器 - ADC 10 Bit 40 MSPS Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1041IPWG4 | 功能描述:模數轉換器 - ADC 10 Bit 40 MSPS Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1041IPWR | 功能描述:模數轉換器 - ADC 10 Bit 40 MSPS Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1041IPWRG4 | 功能描述:模數轉換器 - ADC 10 Bit 40 MSPS Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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