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參數資料
型號: THS1041IPW
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝: GREEN, PLASTIC, TSSOP-28
文件頁數: 28/41頁
文件大小: 810K
代理商: THS1041IPW
THS1041
SLAS289C OCTOBER 2001 REVISED OCTOBER 2004
34
www.ti.com
APPLICATION INFORMATION
definitions
D Integral nonlinearity (INL)—Integral nonlinearity refers to the deviation of each individual code from a line
drawn from zero to full scale. The point used as zero occurs 1/2 LSB before the first code transition. The
full-scale point is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from
the center of each particular code to the true straight line between these two endpoints.
D Differential nonlinearity (DNL)—An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL
is the deviation from this ideal value. Therefore this measure indicates how uniform the transfer function
step sizes are. The ideal step size is defined here as the step size for the device under test (i.e., (last
transition level – first transition level)
÷ (2n – 2)). Using this definition for DNL separates the effects of gain
and offset error. A minimum DNL better than –1 LSB ensures no missing codes.
D Zero-error—Zero-error is defined as the difference in analog input voltage—between the ideal voltage and
the actual voltage—that switches the ADC output from code 0 to code 1. The ideal voltage level is
determined by adding the voltage corresponding to 1/2 LSB to the bottom reference level. The voltage
corresponding to 1 LSB is found from the difference of top and bottom references divided by the number
of ADC output levels (1024).
D Full-scale error—Full-scale error is defined as the difference in analog input voltage—between the ideal
voltage and the actual voltage—that will switch the ADC output from code 1022 to code 1023. The ideal
voltage level is determined by subtracting the voltage corresponding to 1.5 LSB from the top reference level.
The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by
the number of ADC output levels (1024).
D Wake-up time—Wake-up time is from the power-down state to accurate ADC samples being taken and is
specified for MODE = AGND with external reference sources applied to the device at the time of release
of power-down, and an applied 40-MHz clock. Circuits that need to power up are the bandgap, bias
generator, SHPGA, and ADC.
D Power-up time—Power-up time is from the power-down state to accurate ADC samples being taken and
is specified for MODE = AVDD/2 or AVDD and an applied 40-MHz clock. Circuits that need to power up
include VREF reference generation (A1), bias generator, ADC, the SHPGA, and the on-chip ADC reference
generator (A2).
D Aperture delay—The delay between the 50% point of the rising edge of the clock and the instant at which
the analog input is sampled.
D Aperture uncertainty (Jitter)—The sample-to-sample variation in aperture delay.
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THS1041IPWR 功能描述:模數轉換器 - ADC 10 Bit 40 MSPS Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
THS1041IPWRG4 功能描述:模數轉換器 - ADC 10 Bit 40 MSPS Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
THS10420RJ 功能描述:線繞電阻器 - 底架安裝 THS10 420R 5% RoHS:否 制造商:Vishay/Dale 電阻:7 Ohms 容差:1 % 功率額定值:100 W 溫度系數:50 PPM / C 系列:RH 工作溫度范圍:- 55 C to + 250 C 尺寸:46.02 mm Dia. x 46.02 mm W x 88.9 mm L x 44.45 mm H 封裝:Bulk 產品:Power Resistors Wirewound Aluminum Housed
THS10470RJ 功能描述:線繞電阻器 - 底架安裝 THS10 470R 5% RoHS:否 制造商:Vishay/Dale 電阻:7 Ohms 容差:1 % 功率額定值:100 W 溫度系數:50 PPM / C 系列:RH 工作溫度范圍:- 55 C to + 250 C 尺寸:46.02 mm Dia. x 46.02 mm W x 88.9 mm L x 44.45 mm H 封裝:Bulk 產品:Power Resistors Wirewound Aluminum Housed
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