- 您現在的位置：買賣IC網 > PDF目錄98218 > THS1041IPWG4 (TEXAS INSTRUMENTS INC) 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 PDF資料下載
參數資料
| 型號： | THS1041IPWG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, TSSOP-28 |
| 文件頁數： | 21/41頁 |
| 文件大?。?/td> | 810K |
| 代理商： | THS1041IPWG4 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁
THS1041
SLAS289C OCTOBER 2001 REVISED OCTOBER 2004
28
www.ti.com
APPLICATION INFORMATION
driving the THS1041 analog inputs
driving the clock input
Obtaining good performance from the THS1041 requires care when driving the clock input.
Different sections of the sample-and-hold and ADC operate while the clock is low or high. The user should
ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as much time as
possible in which to operate.
The CLK pin should also be driven from a low jitter source for best dynamic performance. To maintain low jitter
at the CLK input, any clock buffers external to the THS1041 should have fast rising edges. Use a fast logic family
such as AC or ACT to drive the CLK pin, and consider powering any clock buffers separately from any other
logic on the PCB to prevent digital supply noise appearing on the buffered clock edges as jitter.
As the CLK input threshold is nominally around AVDD/2, any clock buffers need to have an appropriate supply
voltage to drive above and below this level.
driving the sample and hold inputs
driving the AIN+ and AIN pins
Figure 42 shows an equivalent circuit for the THS1041 AIN+ and AIN pins. The load presented to the system
at the AIN pins comprises the switched input sampling capacitor, CSample, and various stray capacitances, C1
and C2.
C1
8 pF
AVDD
AGND
CLK
C2
1.2 pF
CSample
VCM = AIN+/AIN Common Mode Voltage
AIN
_
+
Figure 42. Equivalent Circuit for Analog Input Pins AIN+ and AIN
The input current pulses required to charge CSample and C2 can be time averaged and the switched capacitor
circuit modelled as an equivalent resistor:
R
IN2 +
1
C
S
f
CLK
where CS is the sum of CSample and C2. This model can be used to approximate the input loading versus source
resistance for high impedance sources.
(14)
相關PDF資料 |
PDF描述 |
|---|---|
| THS1050CPHP | 1-CH 10-BIT DELTA-SIGMA ADC, PARALLEL ACCESS, PQFP48 |
| THS1050IPHP | 1-CH 10-BIT DELTA-SIGMA ADC, PARALLEL ACCESS, PQFP48 |
| THS1050C | 1-CH 10-BIT DELTA-SIGMA ADC, PARALLEL ACCESS, PQFP48 |
| THS1050I | 1-CH 10-BIT DELTA-SIGMA ADC, PARALLEL ACCESS, PQFP48 |
| THS1060CPHP | 1-CH 10-BIT DELTA-SIGMA ADC, PARALLEL ACCESS, PQFP48 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| THS1041IPWR | 功能描述:模數轉換器 - ADC 10 Bit 40 MSPS Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1041IPWRG4 | 功能描述:模數轉換器 - ADC 10 Bit 40 MSPS Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS10420RJ | 功能描述:線繞電阻器 - 底架安裝 THS10 420R 5% RoHS:否 制造商:Vishay/Dale 電阻:7 Ohms 容差:1 % 功率額定值:100 W 溫度系數:50 PPM / C 系列:RH 工作溫度范圍:- 55 C to + 250 C 尺寸:46.02 mm Dia. x 46.02 mm W x 88.9 mm L x 44.45 mm H 封裝:Bulk 產品:Power Resistors Wirewound Aluminum Housed |
| THS10470RJ | 功能描述:線繞電阻器 - 底架安裝 THS10 470R 5% RoHS:否 制造商:Vishay/Dale 電阻:7 Ohms 容差:1 % 功率額定值:100 W 溫度系數:50 PPM / C 系列:RH 工作溫度范圍:- 55 C to + 250 C 尺寸:46.02 mm Dia. x 46.02 mm W x 88.9 mm L x 44.45 mm H 封裝:Bulk 產品:Power Resistors Wirewound Aluminum Housed |
| THS10470RJ | 制造商:TE Connectivity 功能描述:RESISTOR WIREWOUND 470OHM 10W 5% |
發布緊急采購，3分鐘左右您將得到回復。