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參數資料
| 型號： | THS1041IPWR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, TSSOP-28 |
| 文件頁數： | 19/41頁 |
| 文件大小： | 810K |
| 代理商： | THS1041IPWR |
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THS1041
SLAS289C OCTOBER 2001 REVISED OCTOBER 2004
26
www.ti.com
PRINCIPLES OF OPERATION
power management
In power-sensitive applications (such as battery-powered systems) where the THS1041 ADC is not required
to convert continuously, power can be saved between conversion intervals by placing the THS1041 into
power-down mode. This is achieved by setting bit 3 (PWDN) of the control register to 1. In power-down mode,
the device typically consumes less than 0.1 mW. Power-down mode is exited by resetting control register bit
3 to 0. On power up, typical wake-up and power-up times apply. See power supply section.
In systems where the ADC must run continuously, but where the clamp is not required, the supply current can
be reduced by approximately 1.2 mA by setting the control register bit 6 (CLDIS) to 1, which disables the clamp
circuit. Similarly, when REFSENSE is tied to AVDD, the reference generator is disabled and supply current
reduced by approximately 1.2 mA.
output format and digital I/O
While the OE pin is held low, ADC conversion results are output at pins I/O0 (LSB) to I/O9 (MSB). The ADC input
over-range indicator is output at pin OVR. OVR is also disabled when OE is held high.
The default ADC output data format is unsigned binary (output codes 0 to 1023). The output format can be
switched to 2s complement (output codes 512 to 511) by setting control register bit 5 (TWOC) to 1.
writing to the internal registers through the digital I/O bus
Pulling pin OE high disables the I/O and OVR pin output drivers, placing the driver outputs in a high impedance
state. This allows control register data to be loaded into the THS1041 by presenting it on the I/O0 to I/O9 pins
and pulsing the WR pin high then low to latch the data into the chosen control or DAC register.
Figure 41 shows an example register write cycle where the clamp DAC code is set to 10F (hex) by writing to
clamp registers 1 and 2 (see the register map in Table 2). Pins I/O0 to I/O7 are driven to the clamp DAC code
lower byte (0F hex), and pins I/08 and I/O9 are both driven to 0 to select clamp register 1 as the data destination.
The clamp low-byte data is then loaded into this register by pulsing WR high. The top 2 bits of the DAC word
are then loaded by driving 01(hex) on pins I/O0 to I/O7 and by driving pin I/O8 to 1 and pin I/O9 to 0 to select
clamp register 2 as the data destination. WR is pulsed a second time to latch this second control word into clamp
register 2. Interface timing parameters are given in Figures 1 and 2.
OE
WR
I/O (09)
ADC Output
Input 00F
Input 101
ADC Output
Load 0F Into
REGISTER 0
Load 01 Into
REGISTER 1
Figure 41. Example Register Write Cycle to Clamp DAC Register
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相關代理商/技術參數 |
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| THS1041IPWRG4 | 功能描述:模數轉換器 - ADC 10 Bit 40 MSPS Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS10420RJ | 功能描述:線繞電阻器 - 底架安裝 THS10 420R 5% RoHS:否 制造商:Vishay/Dale 電阻:7 Ohms 容差:1 % 功率額定值:100 W 溫度系數:50 PPM / C 系列:RH 工作溫度范圍:- 55 C to + 250 C 尺寸:46.02 mm Dia. x 46.02 mm W x 88.9 mm L x 44.45 mm H 封裝:Bulk 產品:Power Resistors Wirewound Aluminum Housed |
| THS10470RJ | 功能描述:線繞電阻器 - 底架安裝 THS10 470R 5% RoHS:否 制造商:Vishay/Dale 電阻:7 Ohms 容差:1 % 功率額定值:100 W 溫度系數:50 PPM / C 系列:RH 工作溫度范圍:- 55 C to + 250 C 尺寸:46.02 mm Dia. x 46.02 mm W x 88.9 mm L x 44.45 mm H 封裝:Bulk 產品:Power Resistors Wirewound Aluminum Housed |
| THS10470RJ | 制造商:TE Connectivity 功能描述:RESISTOR WIREWOUND 470OHM 10W 5% |
| THS1047RJ | 功能描述:線繞電阻器 - 底架安裝 THS10 47R 5% RoHS:否 制造商:Vishay/Dale 電阻:7 Ohms 容差:1 % 功率額定值:100 W 溫度系數:50 PPM / C 系列:RH 工作溫度范圍:- 55 C to + 250 C 尺寸:46.02 mm Dia. x 46.02 mm W x 88.9 mm L x 44.45 mm H 封裝:Bulk 產品:Power Resistors Wirewound Aluminum Housed |
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