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參數資料
| 型號： | THS1206CDAG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 4-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| 封裝： | GREEN, PLASTIC, TSSOP-32 |
| 文件頁數： | 9/43頁 |
| 文件大小： | 722K |
| 代理商： | THS1206CDAG4 |
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THS1206
SLAS217H – MAY 1999 – REVISED JULY 2003#
www.ti.com
17
Table 2 shows the maximum conversion rate in the single conversion mode.
Table 2. Maximum Conversion Rate in Single Conversion Mode(1)
CHANNEL CONFIGURATION
NUMBER OF
CHANNELS
MAXIMUM CONVERSION
RATE PER CHANNEL
1 single-ended channel
1
3 MSPS
2 single-ended channels
2
2 MSPS
3 single-ended channels
3
1.5 MSPS
4 single-ended channels
4
1.2 MSPS
1 differential channel
1
3 MSPS
2 differential channels
2
2 MSPS
1 single-ended and 1 differential channel
2
2 MSPS
2 single-ended and 1 differential channels
3
1.5 MSPS
(1) Maximum conversion rate with respect to the typical internal oscillator speed (i.e.: 6 MSPS * (tc/t2).
SINGLE CONVERSION MODE
In single conversion mode, a single conversion of the selected analog input channels is performed. The single conversion
mode is selected by setting bit 1 of control register 0 to 1.
A single conversion is initiated by pulsing the CONVST input. On the falling edge of CONVST, the sample and hold stages
of the selected analog inputs are placed into hold simultaneously, and the conversion sequence for the selected channels
is started.
The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. The signal DATA_AV
(data available) becomes active when the trigger level is reached and indicates that the converted sample(s) is (are) written
into the FIFO and can be read out. The trigger level in the single conversion mode can be selected according to Table 13.
Figure 1 shows the timing of the single conversion mode. In this mode, up to four analog input channels can be selected
to be sampled simultaneously (see Table 2).
CONVST
AIN
Sample N
t1
td(A)
t2
tDATA_AV
DATA_AV,
Trigger Level = 1
Figure 24. Timing of Single Conversion Mode
The time (t2) between consecutive starts of single conversions is dependent on the number of selected analog input
channels. The time tDATA_AV, until DATA_AV becomes active is given by: tDATA_AV = tpipe + n × tc. This equation is valid for
a trigger level which is equivalent to the number of selected analog input channels. For all other trigger level conditions refer
to the timing specifications of single conversion mode.
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相關代理商/技術參數 |
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|---|---|
| THS1206CDAR | 功能描述:模數轉換器 - ADC 12-Bit 6 MSPS Quad Channel RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1206CDARG4 | 功能描述:模數轉換器 - ADC 12-Bit 6 MSPS Quad Channel RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1206DA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS |
| THS1206-EP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:12-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS |
| THS1206EVM | 制造商:Texas Instruments 功能描述:12-BIT 6MSPS QUAD CH. LOW POWER ADC EVM - Bulk 制造商:Texas Instruments 功能描述:THS1206 EVAL MODULE |
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