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參數(shù)資料
| 型號： | THS1209CDAR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| 封裝： | GREEN, PLASTIC, TSSOP-32 |
| 文件頁數(shù)： | 15/33頁 |
| 文件大小： | 312K |
| 代理商： | THS1209CDAR |
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THS1209
SLAS288B – JULY 2000 – REVISED DECEMBER 2002
www.ti.com
22
Control Register 1 (see Table 8)
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
1
RBACK
OFFSET
BIN/2s
R/W
RES
SRST
RESET
Table 11. Control Register 1 Bit Functions
BITS
RESET
VALUE
NAME
FUNCTION
0
RESET
Reset
Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values.
To bring the device out of reset, a 0 has to be written into this bit.
1
0
SRST
Writing a 1 into this bit resets the sync generator. When running in multichannel mode, this must be set during the
configuration cycle.
2, 3
0,0
RES
Always write 0
4
1
RES
Always write 0
5
1
RES
Always write 0
6
0
R/W
R/W, RD/WR selection
Bit 6 of control register 1 controls the function of the inputs RD and WR. When bit 6 in control register 1 is set to
1, WR becomes a R/W input and RD is disabled. From now on a read is signalled with R/W high and a write with
R/W as a low signal. If bit 6 in control register 1 is set to 0, the input RD becomes a read input and the input WR
becomes a write input.
7
0
BIN/2s
Complement select
If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of
control register 1 is set to 1, the output value of the ADC is in binary format. Refer to Table 2 through Table 5.
8
0
OFFSET
Offset cancellation mode
Bit 8 = 0
→ normal conversion mode
Bit 8 = 1
→ offset calibration mode
If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a conver-
sion. The conversion result is stored in an offset register and subtracted from all conversions in order to
reduce the offset error.
9
0
RBACK
Debug mode
Bit 9 = 0
→ normal conversion mode
Bit 9 = 1
→ enable debug mode
When bit 9 of control register 1 is set to 1, debug mode is enabled. In this mode, the contents of control register 0
and control register 1 can be read back. The first read after bit 9 is set to 1 contains the value of control register 0.
The second read after bit 9 is set to 1 contains the value of control register 1. To bring the device back into normal
conversion mode, this bit has to be set back to 0 by writing again to control register 1.
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