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參數資料
| 型號： | THS1215IDWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, SOIC-28 |
| 文件頁數： | 21/24頁 |
| 文件大小： | 539K |
| 代理商： | THS1215IDWRG4 |
www.ti.com
ELECTRICAL CHARACTERISTICS (CONTINUED)
THS1215
SLAS292A – MARCH 2001 – REVISED MARCH 2004
over recommended operating conditions (AV
DD = DVDD = 3.3 V, fs = 15 MHz/50% duty cycle, MODE = 1, 1-V input span,
internal reference, T
min to Tmax) (unless otherwise noted)
REFT, REFB REFERENCE VOLTAGE (all supplies = 3.3 V)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
INTERNAL REFERENCE(1)
VREFT
Upper reference voltage
2.15
V
VREFB Lower reference voltage
1.15
V
VREF
Differential reference voltage, VREFT – VREFB
0.95
1
1.05
V
Differential reference voltage, VREFT – VREFB accuracy
–5%
5%
EXTERNAL REFERENCE
Externally applied VREFT reference voltage range
2
2.5
V
Externally applied VREFB reference voltage range
1.05
1.3
V
Externally applied (VREFT – VREFB) reference voltage range
0.75
1.05
V
External mode VREFT to VREFB impedance
9
k
INTERNAL EXTERNAL REFERENCE
CT
VREFT decoupling capacitor value
0.1
F
CB
VREFB decoupling capacitor value
0.1
F
CTB
Decoupling capacitor VREFT to VREFB
10
F
DC ACCURACY (LINEARITY)
Number of missing codes
All modes
0
codes
DNL
Differential nonlinearity
All modes
±0.43
±0.9
LSB
INL
Integral nonlinearity
All modes
±0.6
±2.5
LSB
Offset error
All modes
1.4
2.2
%FSR
Gain error
All modes
2.2
3.5
%FSR
DYNAMIC PERFORMANCE (all supplies = 3.3 V)
ENOB
Effective number of bits
fi = 3.58 MHz
10.7
11.1
Bits
THD
Total harmonic distortion
fi = 3.58 MHz
–81.2
dB
SNR
Signal-to-noise ratio
fi = 3.58 MHz
67.4
68.9
dB
SINA
Signal-to-noise + distortion
fi = 3.58 MHz
66
68.6
dB
D
SFDR
Spurious free dynamic range
fi = 3.58 MHz
72
81.7
dB
Analog input bandwidth
180
MHz
Differential phase, DP
0.12
degree
G(diff)
Differential gain
0.01%
TIMING (all supplies = 3.3 V)
fCLK
Clock frequency(2)
5
15
MHz
Clock duty cycle
45%
50%
55%
td(O)
Output delay time
6
19
ns
td(PZ)
Delay time, output disable to Hi-Z output
3.2
ns
td(EN)
Delay time, output enable to output valid
16
19
ns
Latency
4
5
cycles
(1)
The internal reference voltage is not intended for use driving off chip.
(2)
The clock frequency may be extended down to 5 MHz without degradation in specified performance.
6
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