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參數(shù)資料
| 型號(hào)： | THS1215IPWR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, TSSOP-28 |
| 文件頁(yè)數(shù)： | 17/22頁(yè) |
| 文件大小： | 391K |
| 代理商： | THS1215IPWR |
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RECOMMENDED OPERATING CONDITIONS
THS1215
SLAS292A – MARCH 2001 – REVISED MARCH 2004
over operating free-air temperature range, T
A (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
Supply voltage
AVDD
3.0
3.3
3.6
V
DVDD
ANALOG AND REFERENCE INPUTS
VREFT
fCLK = 5 MHz to 15 MHz
2.0
2.15
2.5
Reference input voltage
V
VREFB
fCLK = 5 MHz to 15 MHz
1.05
1.15
1.3
Reference voltage differential, VREFT – VREFB
fCLK = 5 MHz to 15 MHz
0.95
1.0
1.05
V
CON1 = 0, CON0 = 1
–1.0
1.0
V
Analog input voltage differential, (AIN+) – (AIN–)(1)
CON1 = 1, CON0 = 0
–2.0
2.0
V
Analog input capacitance, Ci
10
pF
Clock input(2)
0
AVDD
V
DIGITAL OUTPUTS
Minimum digital output load resistance, RL
100
k
Maximum digital output load capacitance, Ci
0
10
15
pF
DIGITAL INPUTS
High-level input voltage, VIH
2.4
DVDD
V
Low-level input voltage, VIL
DGND
0.8
V
Clock frequency, fCLK, See Note
(3)
5
30
MHz
Clock pulse duration, tW(CLKL), tW(CLKH)
fCLK = 15 MHz
30
33.3
36.7
ns
TH1215
0
70
°C
Operating free-air temperature, TA
TJ1215
–40
85
(1)
Based on VREFT – VREFB = 1.0 V, varies proportional to the VREFT – VREFB value. AIN+ and AIN– inputs must always be greater than 0 V
and less than AVDD.
(2)
Clock pin is referenced to AGND and powered by AVDD.
(3)
Clock frequency can be extended to this range without degradation of performance.
4
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