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參數(shù)資料
| 型號： | THS1240C |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT DELTA-SIGMA ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | POWER, PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 16/19頁 |
| 文件大小： | 424K |
| 代理商： | THS1240C |
THS1240
12-BIT 40 MSPS IF SAMPLING COMMUNICATIONS
ANALOG-TO-DIGITAL CONVERTER
SLAS279A – JUNE 2000 – REVISED AUGUST 2000
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
definitions of specifications
analog bandwidth
The analog input frequency at which the spectral power of the fundamental frequency of a large input signal
is reduced by 3 dB.
aperture delay
The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is
sampled.
aperture uncertainity (jitter)
The sample-to-sample variation in aperture delay
differential nonlinearity
The deviation of any output code from the ideal width of 1 LSB.
integral nonlinearity
The deviation of the transfer function from an end-point adjusted reference line measured in fractions of 1 LSB.
Also the integral of the DNL curve.
clock pulse width/duty cycle
Pulse width high is the minimum amount of time that the clock pulse should be left in logic 1 state to achieve
rated performance; pulse width low is the minimum time clock pulse should be left in low state. At a given clock
rate, these specs define acceptable clock duty cycles.
offset error
The difference between the analog input voltage at which the ADC output changes from mid-scale to 1 LSB
above mid-scale, and the ideal voltage at which this transition should occur.
gain error
The difference between the analog input voltage at which the ADC output changes from full-scale to 1 LSB below
full scale, and the ideal voltage at which this transition should occur, minus the offset error
Gain Error
+ 100%x
2
* V
IN
) * VIN_
2V
@Code 4096
total harmonic distortion
The ratio of the power of the fundamental to a given harmonic component reported in dBc.
output delay
The delay between the 50% point of the falling edge of the clock and the time when all output data bits are within
valid logic levels (not including pipeline delay).
signal-to-noise-and distortion (SINAD)
When tested with a single tone, the ratio of the signal power to the sum of the power of all other spectral
components, excluding dc, referenced to full scale.
signal-to-noise ratio (SNR)
When tested with a single tone, the ratio of the signal power to the sum of the power of all other power spectral
components, excluding dc and the first 9 harmonics, referenced to full scale.
effective number of bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the effective number of bits, using the following formula,
ENOB
+
(SINAD
* 1.76)
6.02
spurious-free dynamic range (SFDR)
The ratio of the signal power to the power of the worst spur, excluding dc. The worst spurious component may
or may not be a harmonic. The ratio is reported in dBc (that is, degrades as signal levels are lowered).
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| THS1240CPHP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| THS1240IPHP | 功能描述:IC 12 BIT ADC 40 MSPS 48-HTQFP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| THS125 | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:HIGH STABILITY MOTOR CONTROL. DIGITAL TACHOMETER. CRANK SHAFT POSITION SENSOR. |
| THS126 | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:HIGH STABILITY MOTOR CONTROL. DIGITAL TACHOMETER. CRANK SHAFT POSITION SENSOR. |
| THS126(F) | 制造商:Toshiba 功能描述:Cut Tape |
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