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參數資料
| 型號： | THS1401QPFB |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | PLASTIC, TQFP-48 |
| 文件頁數： | 14/30頁 |
| 文件大小： | 475K |
| 代理商： | THS1401QPFB |
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THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA
SLAS248B – DECEMBER 1999 – REVISED JANUARY 2001
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
internal/external reference operation
The THS1401/3/8 ADC can either be operated using the built-in band gap reference or using an external
precision reference in case very high dc accuracy is needed.
The REF+ and REF+ outputs are given by:
REF
)+ VBG 1 ) 2
3
and REF–
+ VBG 1– 2
3
If the built-in reference is used, VBG equals 1.5 V which results in REF+ = 2.5 V, REF– = 0.5 V and
REF =
2V.
The internal reference can be disabled by writing 1 to D12 (REF) in the control register (address 3). The band
gap reference is then disconnected and can be substituted by a voltage on the VBG pin.
programmable gain amplifier
The on-chip programmable gain amplifier (PGA) has eight gain settings. The gain can be changed by writing
to the PGA gain register (address 1). The range is 0 to 7dB in steps of one dB.
out of range indication
The OV output of the ADC indicates an out of range condition. Every time the difference on the analog inputs
exceeds the differential reference, this signal is asserted. This signal is updated the same way as the digital data
outputs and therefore subject to the same pipeline delay.
offset compensation
With the offset register it is possible to automatically compensate system offset errors, including errors caused
by additional signal conditioning circuitry. If the offset compensation is enabled (D7 (OFF) in the control register),
the value in the offset register (address 2) is automatically subtracted from the output of the ADC.
In order to set the correct value of the offset compensation register, the ADC result when the input signal is 0
must be read by the host processor and written to the offset register (address 2).
test modes
The ADC core operation can be tested by selecting one of the available test modes (see control register
description). The test modes apply various voltages to the differential input depending on the setting in the
control register.
digital I/O
The digital inputs and outputs of the THS1401/3/8 ADC are 3-V CMOS compatible. In order to avoid current
feed back errors, the capacitive load on the digital outputs should be as low as possible (50 pF max). Series
resistors (100
) on the digital outputs can improve the performance by limiting the current during output
transitions.
The parallel interface of the THS1401/3/8 ADC features 3-state buffers, making it possible to directly connect
it to a data bus. The output buffers are enabled by driving the OE input low.
Refer to the read and write timing diagrams in the parameter measurement information section for information
on read and write access.
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相關代理商/技術參數 |
參數描述 |
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| THS1401QPHP | 功能描述:IC A/D 14BIT 1MSPS 1-CH 48HTQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
| THS1401QPHPEP | 功能描述:模數轉換器 - ADC Mil Enhanc 14B 1/3/8 MSPS DSP Comp ADC RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| THS1403 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:14-Bit, 1/3/8 MSPS, DSP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA |
| THS1403CPFB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| THS1403-EP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA |
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