- 您現(xiàn)在的位置：買賣IC網 > PDF目錄98228 > THS5651IPWLE (TEXAS INSTRUMENTS INC) PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28 PDF資料下載
參數(shù)資料
| 型號： | THS5651IPWLE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 10-BIT DAC, PDSO28 |
| 封裝： | PLASTIC, TSSOP-28 |
| 文件頁數(shù)： | 5/28頁 |
| 文件大小： | 702K |
| 代理商： | THS5651IPWLE |
第1頁第2頁第3頁第4頁當前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
THS5651
10-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS197A – JUNE 1999
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
The THS5651 architecture is based on current steering, combining high update rates with low power
consumption. The CMOS device consists of a segmented array of PMOS transistor current sources, which are
capable of delivering a full-scale current up to 20 mA. High-speed differential current switches direct the current
of each current source to either one of the output nodes, IOUT1 or IOUT2. The complementary output currents
thus enable differential operation, canceling out common mode noise sources (on-chip and PCB noise), dc
offsets, even order distortion components, and increase signal output power by a factor of two. Major
advantages of the segmented architecture are minimum glitch energy, excellent DNL, and very good dynamic
performance. The DAC’s high output impedance of >300 k
and fast switching result in excellent dynamic
linearity (spurious free dynamic range SFDR).
The full-scale output current is set using an external resistor RBIAS in combination with an on-chip bandgap
voltage reference source (1.2 V) and control amplifier. The current IBIAS through resistor RBIAS is mirrored
internally to provide a full-scale output current equal to 32 times IBIAS. The full-scale current can be adjusted
from 20 mA down to 2 mA.
data interface and timing
The THS5651 comprises separate analog and digital supplies, i.e. AVDD and DVDD. The digital supply voltage
can be set from 5.5 V down to 3 V, thus enabling flexible interfacing with external logic. The THS5651 provides
two operating modes, as shown in Table 1. Mode 0 (mode pin connected to DGND) supports a straight binary
input data word format, whereas mode 1 (mode pin connected to DVDD) sets a twos complement input
configuration.
Figure 20 shows the timing diagram. Internal edge-triggered flip-flops latch the input word on the rising edge
of the input clock. The THS5651 provides for minimum setup and hold times (> 1 ns), allowing for noncritical
external interface timing. Conversion latency is one clock cycle for both modes. The clock duty cycle can be
chosen arbitrarily under the timing constraints listed in the digital specifications table. However, a 50% duty cycle
will give optimum dynamic performance. Figure 21 shows a schematic of the equivalent digital inputs of the
THS5651, valid for pins D9–D0, SLEEP, and CLK. The digital inputs are CMOS-compatible with logic thresholds
of DVDD/2 ±20%. Since the THS5651 is capable of being updated up to 100 MSPS, the quality of the clock and
data input signals are important in achieving the optimum performance. The drivers of the digital data interface
circuitry should be specified to meet the minimum setup and hold times of the THS5651, as well as its required
min/max input logic level thresholds. Typically, the selection of the slowest logic family that satisfies the above
conditions will result in the lowest data feed-through and noise. Additionally, operating the THS5651 with
reduced logic swings and a corresponding digital supply (DVDD) will reduce data feed-through. Note that the
update rate is limited to 67 MSPS for a digital supply voltage DVDD of 3 V to 3.6 V.
相關PDF資料 |
PDF描述 |
|---|---|
| THS5661AIDWG4 | PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 12-BIT DAC, PDSO28 |
| THS5661AIDWRG4 | PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 12-BIT DAC, PDSO28 |
| THS5661AIPWRG4 | PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 12-BIT DAC, PDSO28 |
| THS5661AIPW | PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 12-BIT DAC, PDSO28 |
| THS5661AIDWR | PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 12-BIT DAC, PDSO28 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| THS5651PW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT, 100 MSPS, CommsDACE DIGITAL-TO-ANALOG CONVERTER |
| THS5661 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:12-BIT, 100 MSPS, CommsDACE DIGITAL-TO-ANALOG CONVERTER |
| THS5661A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:12-BIT, 125 MSPS, CommsDACE DIGITAL-TO-ANALOG CONVERTER |
| THS5661ADW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:12-BIT, 125 MSPS, CommsDACE DIGITAL-TO-ANALOG CONVERTER |
| THS5661AIDW | 功能描述:數(shù)模轉換器- DAC 12-Bit 125 MSPS CommsDAC RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復。