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參數資料
型號: THS8135-240IPHP
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PQFP48
封裝: POWER, TQFP-48
文件頁數: 21/24頁
文件大小: 546K
代理商: THS8135-240IPHP
THS8135
TRIPLE 10-BIT, 80/240 MSPS VIDEO DAC WITH TRI-LEVEL SYNC AND VIDEO
(ITU-R.BT601) – COMPLIANT FULL SCALE RANGE
SLVSXXXX—10/02/00 3:44 PM
7
Copyright 2000 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
1
Generic mode. Blanking override inactive.
1
0
1
Generic mode. Blanking override active. Blanking level position is according to
the codes of Table 7, however no dc bias is present on the DAC outputs
1
0
Video mode. Blanking override inactive.
1
0
Video mode. Blanking override active. Blanking level position is according to the
codes of Table 7, with dc bias present on the DAC outputs as shown in Figure 7.
0
X
0
Video mode. Negative sync inserted.
0
X
1
Video mode. Positive sync inserted.
Device Configuration using M1 & M2
The configuration signals M1 and M2 are both
1 sampled on the 2nd rising edge of the CLK input signal after a L->H
or H->L transition on /SYNC. Depending on the polarity of this last transition on /SYNC, M1 and M2 are interpreted
differently by THS8135, as shown in Table 4.
Table 4: Interpretation of M1
If
last
event on
/SYNC
is:
Then M1 is interpreted
on 2
nd CLK rising edge
following this event as:
Description
H->L
BLNK_INT
Sets operation with Full or Video (ITU-R.BT601)- compliant code Input Range.
Selection available in both generic and video modes i.e. the full-scale range is
reached from either the 0-1023 code range or the code range of Table 8.
L->H
M1_INT
Sets device operation mode. See Tables 6 & 7.
Table 5: Interpretation of M2
If
last
event on
/SYNC
is:
Then M2 is interpreted
on 2
nd CLK rising edge
following this event as:
Description
H->L
INS3_INT
Sets Sync Insertion mode: /SYNC low enables sync generation on 1
(INS3_INT=L) or all 3 (INS3_INT=H) DAC outputs. SYNC_T determines the
sync polarity.
L->H
M2_INT
Sets device operation mode. See Tables 7 & 8.
Selection of Color Space and Input Formatter Mode
1 In THS8133, only M2 is a sampled signal while M1 is continuously interpreted. By doing so here, the additional
input control signal BLNK_INT is generated. See paragraph on backward compatibility with THS8133.
相關PDF資料
PDF描述
THS8135-80CPHP PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PQFP48
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相關代理商/技術參數
參數描述
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