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參數(shù)資料
| 型號： | THS8136PHP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.015 us SETTLING TIME, 10-BIT DAC, PQFP48 |
| 封裝： | PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 18/18頁 |
| 文件大小： | 377K |
| 代理商： | THS8136PHP |
www.ti.com
SLES236A – NOVEMBER 2008 – REVISED DECEMBER 2010
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
AVDD to AVSS
–0.5 V to 3.6 V
Supply voltage
DVDD to DVSS
–0.5 V to 1.95 V
AVSS to DVSS
–0.5 to 0.5 V
Digital input voltage range to DVSS
–0.5 V to (DVDD + 0.5) V
TA
Operating free-air temperature range
–40°C to 85°C
Tstg
Storage temperature range
–55°C to 150°C
Human-body model (HBM)(3), All pins
>2000 V
VESD
ESD stress voltage(2)
Charged-device model (CDM)(4), All pins
>500 V
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.
(3)
Level listed is the passing level per ANSI/ESDA/JEDEC JS-001-2010 and AEC Q100-002 rev D. JEDEC document JEP155 states that
500-V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500-V HBM is possible if
necessary precautions are taken. Pins listed as 2000 V may actually have higher performance.
(4)
Level listed is the passing level per EIA-JEDEC JESD22-C101E and AEC Q100-011 rev B. JEDEC document JEP157 states that 250-V
CDM allows safe manufacturing with a standard ESD control process. Pins listed as 500 V may actually have higher performance.
Corner pins meet the AEC Q100-011 rev B 750-V requirement.
THERMAL SPECIFICATIONS
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
Thermal PAD soldered to 4-layer High-K
29.11
°C/W
PCB
qJA
Junction-to-ambient thermal resistance, still air
Low-K PCB, Thermal PAD not soldered
64.42
°C/W
qJC
Junction-to-case thermal resistance, still air
0.12
Maximum junction temperature for reliable
TJ(MAX)
105
°C
operation
(1)
When split ground planes are used, attach the thermal pad to the analog ground plane.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
Power Supply
AVDD
3
3.3
3.6
V
DVDD
1.65
1.8
1.95
V
Digital and Reference Inputs
VIH
High-level input voltage
1.2
DVDD
V
VIL
Low-level input voltage
DVSS
0.7
V
fCLK
Clock frequency
0
180
MHz
CLK
tw(CLKH)
Pulse duration, clock high
40%
60%
period
CLK
tw(CLKL)
Pulse duration, clock low
40%
60%
period
RFS(nom)
FSADJ resistor(1)
3.8
k
(1)
RFS should be chosen such that the maximum full-scale DAC output current (IFS) does not exceed the maximum stated level. This yields
the nominal output voltage compliance at the nominal load termination of 37.5
.
Copyright 2008–2010, Texas Instruments Incorporated
9
Product Folder Link(s): THS8136
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