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參數資料
| 型號： | TICPAL22V10Z-30IJTL |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | EPICE CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS |
| 中文描述： | EPICE CMOS可編程陣列邏輯電路 |
| 文件頁數： | 1/22頁 |
| 文件大小： | 202K |
| 代理商： | TICPAL22V10Z-30IJTL |
PLASTIC
DUAL-IN-LINE
(NT)
PLASTIC
CHIP CARRIER
(FN)
CERAMIC WINDOWED
DUAL-IN-LINE
(JTL)
TICPAL22V10Z-25C, TICPAL22V10Z-30I
EPIC
CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1992, Texas Instruments Incorporated
1
PRODUCTION DATA information is current as of publication date.
standard warranty. Production processing does not necessarily include
testing of all parameters.
24-Pin Advanced CMOS PLD
Virtually Zero Standby Power
Propagation Delay Time:
I, I/O to I/O in the Turbo Mode
-25C . . . 25 ns Max
-30I . . . 30 ns Max
I, I/O to I/O in the Zero-Power Mode
-25C . . . 35 ns Max
-30I . . . 40 ns Max
CLK to Q
-25C . . . 15 ns Max
-30I . . . 20 ns Max
Variable Product Term Distribution Allows
More Complex Functions to Be
Implemented
Each Output Is User-Programmable for
Registered or Combinatorial Operation,
Polarity, and Output Enable Control
Extra Terms Provide Logical Synchronous
Set and Asynchronous Reset Capability
Preload Capability on All Registered
Outputs Allow for Improved Device Testing
UV Light Erasable Cell Technology Allows
for:
Reconfigurable Logic
Reprogrammable Cells
Full Factory Testing for High
Programming Yield
Programmable Design Security Bit
Prevents Copying of Logic Stored in Device
Package Options Include Plastic
Dual-In-Line and Clip Carrier [for
One-Time-Programmable (OTP) Devices]
and Ceramic Dual-In-Line Windowed
Package
.
AVAILABLE OPTIONS
PACKAGE TYPE
TA
RANGE
0
°
C to 75
°
C
–40
°
C to 85
°
C
TICPAL22V10Z-25CJTL
NA
TICPAL22V10Z-25CNT
TICPAL22V10Z-30INT
TICPAL22V10Z-25CFN
TICPAL22V10Z-30IFN
These devices are covered by U.S. Patent 4,410,987.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/I
I
I
I
I
I
I
I
I
I
I
GND
V
CC
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
JTL AND NT PACKAGE
(TOP VIEW)
3 2 1 28 27
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
I
I
I
NC
I
I
I
4
26
14 15 16 1718
I
I
G
N
I
I
I
I
I
C
N
I
I
FN PACKAGE
(TOP VIEW)
NC
–
No internal connection
Pin assignments in operating mode
V
C
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