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參數(shù)資料
| 型號： | TLC1540CDW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 12-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大小： | 162K |
| 代理商： | TLC1540CDW |
TLC1540C, TLC1541C
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS073B – DECEMBER 1995 – REVISED JUNE 1996
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
It is possible to connect SYSTEM CLOCK and I/O CLOCK together in special situations in which controlling-circuitry
points must be minimized. In this case, the following special points must be considered in addition to the requirements
of the normal control sequence previously described.
1.
This device requires the first two clocks to recognize that CS is at a valid low level when the common clock
signal is used as an I/O CLOCK. When CS is recognized by the device to be at a high level, the common clock
signal is used for the conversion clock also.
2.
A low CS must be recognized before the I/O CLOCK can shift in an analog channel address. The device
recognizes a CS transition when the SYSTEM CLOCK terminal receives two positive edges and then a
negative edge. For this reason, after a CS negative edge, the first two clock cycles do not shift in the address.
Also, upon shifting in the address, CS must be raised after the tenth valid (12 total) I/O CLOCK. Otherwise,
additional common-clock cycles are recognized as I/O CLOCK cycles and shift in an erroneous address.
For certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time.
This device accommodates these applications. Although the on-chip sample-and-hold begins sampling upon the
negative edge of the fourth valid I/O CLOCK cycle, the hold function does not initiate until the negative edge of the
tenth valid I/O CLOCK cycle. Thus, the control circuitry can leave the I/O CLOCK signal in its high state during the
tenth valid I/O CLOCK cycle until the moment at which the analog signal must be converted. The TLC1540/TLC1541
continues sampling the analog input until the eighth valid falling edge of the I/O CLOCK. The control circuitry or
software then immediately lowers the I/O CLOCK signal and holds the analog signal at the desired point in time and
starts the conversion.
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| TLC1541CDW | 11-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| TLC1541IDWR | 11-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC1541 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 INPUTS |
| TLC1541CDW | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10bit A/D w/Ser In RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLC1541CDWG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-Bit 32 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLC1541CDWR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-Bit 32 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLC1541CDWRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-Bit 32 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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