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參數(shù)資料
| 型號： | TLC1542QN |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 11-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 7/36頁 |
| 文件大?。?/td> | 748K |
| 代理商： | TLC1542QN |
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TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10BIT ANALOGTODIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052F MARCH 1992 REVISED JANUARY 2004
15
WWW.TI.COM
PARAMETER MEASUREMENT INFORMATION
timing diagrams (continued)
Access Cycle B
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB
LSB
Previous Conversion Data
MSB
LSB
B3
B2
B1
B0
C3
B9
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
12
3
4
5
6
78
9
10
1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
EOC
Initialize
Low
Level
Hi-Z
See Note B
11
16
(see Note A)
NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS
↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the
minimum CS setup time has elapsed.
B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges of
the internal system clock.
Figure 11. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Shorter Than Conversion)
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| TLC1542QDW | 11-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
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| TLC1543 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS |
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| TLC1543CDB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Hi-Spd A/D Conv RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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