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參數資料
| 型號： | TLC1543QDWREP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 11-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, PLASTIC, SOIC-20 |
| 文件頁數： | 19/25頁 |
| 文件大?。?/td> | 573K |
| 代理商： | TLC1543QDWREP |
TLC1542EP, TLC1543EP
10BIT ANALOGTODIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS152A JANUARY 2004 REVISED FEBRUARY 2006
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
ADDRESS
17
I
Serial address input. A 4-bit serial address selects the desired analog input or test voltage that is to be
converted next. The address data is presented with the MSB first and shifts in on the first four rising edges
of I/O CLOCK. After the four address bits have been read into the address register, this input is ignored for
the remainder of the current conversion period.
A0 A10
1 9,
11, 12
I
Analog signal inputs. The 11 analog inputs are applied to these terminals and are internally multiplexed. The
driving source impedance should be less than or equal to 1 k
.
CS
15
I
Chip select. A high-to-low transition on this input resets the internal counters and controls and enables DATA
OUT, ADDRESS, and I/O CLOCK within a maximum of a setup time plus two falling edges of the internal
system clock. A low-to-high transition disables ADDRESS and I/O CLOCK within a setup time plus two falling
edges of the internal system clock.
DATA OUT
16
O
The 3-state serial output for the A/D conversion result. This output is in the high-impedance state when CS
is high and active when CS is low. With a valid chip select, DATA OUT is removed from the high-impedance
state and is driven to the logic level corresponding to the MSB value of the previous conversion result. The
next falling edge of I/O CLOCK drives this output to the logic level corresponding to the next most significant
bit, and the remaining bits shift out in order with the LSB appearing on the ninth falling edge of I/O CLOCK.
On the tenth falling edge of I/O CLOCK, DATA OUT is driven to a low logic level so that serial interface data
transfers of more than ten clocks produce zeroes as the unused LSBs.
EOC
19
O
End of conversion. This output goes from a high to a low logic level on the trailing edge of the tenth I/O CLOCK
and remains low until the conversion is complete and data is ready for transfer.
GND
10
I
The ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are
with respect to this terminal.
I/O CLOCK
18
I
Input/output clock. This terminal receives the serial I/O CLOCK input and performs the following four
functions:
1) It clocks the four input address bits into the address register on the first four rising edges of the I/O CLOCK
with the multiplex address available after the fourth rising edge.
2) On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplex input begins
charging the capacitor array and continues to do so until the tenth falling edge of I/O CLOCK.
3) It shifts the nine remaining bits of the previous conversion data out on DATA OUT.
4) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock.
REF +
14
I
The upper reference voltage value (nominally VCC) is applied to this terminal. The maximum input voltage
range is determined by the difference between the voltage applied to this terminal and the voltage applied
to the REF terminal.
REF
13
I
The lower reference voltage value (nominally ground) is applied to this terminal.
VCC
20
I
Positive supply voltage
detailed description
With chip select (CS) inactive (high), the ADDRESS and I/O CLOCK inputs are initially disabled and DATA OUT
is in the high-impedance state. When the serial interface takes CS active (low), the conversion sequence begins
with the enabling of I/O CLOCK and ADDRESS and the removal of DATA OUT from the high-impedance state.
The serial interface then provides the 4-bit channel address to ADDRESS and the I/O CLOCK sequence to I/O
CLOCK. During this transfer, the serial interface also receives the previous conversion result from DATA OUT.
I/O CLOCK receives an input sequence that is between 10 and 16 clocks long from the host serial interface.
The first four I/O clocks load the address register with the 4-bit address on ADDRESS, selecting the desired
analog channel, and the next six clocks providing the control timing for sampling the analog input.
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