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參數資料
| 型號： | TLC2543QDWRQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | PLASTIC, SOIC-20 |
| 文件頁數： | 25/25頁 |
| 文件大小： | 413K |
| 代理商： | TLC2543QDWRQ1 |
TLC2543Q1
12BIT ANALOGTODIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS218D NOVEMBER 2003 REVISED MAY 2008
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Access Cycle B
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB
LSB
Previous Conversion Data
MSB
LSB
B7
B6
B5
B4
C7
B11
A11
A10
A9
A8
A7
A6
A5
A4
A1
A0
Hi-Z State
1
2
3
4
5
6
7
8
11
12
1
I/O
CLOCK
DATA
OUT
DATA
INPUT
CS
EOC
(see Note A)
B3
B2
B1
B0
t(conv)
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS
↓ before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 9. Timing for 12-Clock Transfer Using CS With MSB First
Access Cycle B
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB
LSB
Previous Conversion Data
MSB
LSB
B7
B6
B5
B4
C7
B11
A11
A10
A9
A8
A7
A6
A5
A4
A1
A0
Low Level
1
2
3
4
5
6
7
8
11
12
1
I/O
CLOCK
DATA
OUT
DATA
INPUT
CS
EOC
Initialize
(see Note A)
B3
B2
B1
B0
t(conv)
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS
↓ before responding to control input signals.
Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 10. Timing for 12-Clock Transfer Not Using CS With MSB First
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