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參數資料
| 型號： | TLC2554QDR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | PLASTIC, MS-012AC, SOIC-16 |
| 文件頁數： | 27/48頁 |
| 文件大小： | 1072K |
| 代理商： | TLC2554QDR |
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TLC2554, TLC2558
5-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
SLAS220A –JUNE 1999
33
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Rs
ri
VS
VC
Driving Source
TLC2554/58
Ci
VI
VI = Input Voltage at AIN
VS = External Driving Source Voltage
Rs = Source Resistance
ri = Input Resistance (MUX on Resistance)
Ci = Input Capacitance
VC= Capacitance Charging Voltage
Driving source requirements:
Noise and distortion for the source must be equivalent to the resolution of the converter.
Rs must be real at the input frequency.
Figure 37. Equivalent Input Circuit Including the Driving Source
maximum conversion throughput
For a supply voltage of 5 V, if the source impedance is less than 1 k
, and the ADC analog input capacitance
Ci is less than 50 pF, this equates to a minimum sampling time tch(0.5 LSB) of 0.676
s. Since the sampling
time requires 12 SCLKs, the fastest SCLK frequency is 12/tch = 18 MHz.
The minimal total cycle time is given as:
tc
+ tcommand ) tch ) tconv ) td(EOCH–CSL) + 4
1
f (SCLK)
) 12
1
f (SCLK)
) 1.6 ms ) 0.1 ms
+ 16
1
18
MHz
) 1.7 ms + 2.59 ms
This is equivalent to a maximum throughput of 386 KSPS. The throughput can be even higher with a smaller
source impedance.
When source impedance is 100
, the minimum sampling time becomes:
tch (1 2 LSB)
+ Rt
Ci
In(8192)
+ 0.27 ms
The maximum SCLK frequency possible is 12/tch = 44 MHz. Then a 20 MHz clock (maximum SCLK frequency
for the TLC2554/2548 ) can be used. The minimal total cycle time is then reduced to:
tc
+ tcommand ) tch ) tconv ) td(EOCH–CSL) + 4
1
f (SCLK)
) 12
1
f (SCLK)
) 1.6 ms ) 0.1 ms
+ 0.8 ms ) 1.6 ms ) 0.1 ms + 2.5 ms
The maximum throughput is 1/2.5
s = 400 KSPS for this case.
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