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參數資料
| 型號： | TLC2558IPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, PLASTIC, TSSOP-20 |
| 文件頁數： | 26/48頁 |
| 文件大小： | 1072K |
| 代理商： | TLC2558IPWRG4 |
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TLC2554, TLC2558
5-V, 12-BIT, 400 KSPS, 4/8 CHANNEL, LOW POWER,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO POWER DOWN
SLAS220A –JUNE 1999
32
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
simplified analog input analysis
Using the equivalent circuit in Figure 39, the time required to charge the analog input capacitance from 0 to VS
within 1/2 LSB can be derived as follows.
The capacitance charging voltage is given by:
Vc
+ Vs 1–EXP
–tc
Rt
Ci
Where
Rt = Rs + Zi
tc = Cycle time
(1)
The input impedance Zi is 0.5 k
at 5 V. The final voltage to 1/2 LSB is given by:
VC (1 2 LSB)
+ VS–
VS
8192
(2)
Equating equation 1 to equation 2 and solving for cycle time tc gives:
Vs–
VS
8192
+ Vs 1–EXP
–tc
Rt
Ci
(3)
and time to change to 1/2 LSB (minimum sampling time) is:
tch (1 2 LSB)
+ Rt
Ci
In(8192)
Where
In(8192) = 9.011
Therefore, with the values given, the time for the analog input signal to settle is:
tch (1 2 LSB)
+ (Rs ) 0.5 kW)
Ci
In(8192)
(4)
This time must be less than the converter sample time shown in the timing diagrams. This is 12
× SCLKs (if the
sampling mode is short normal sampling mode).
tch (1 2 LSB)
v 12
1
f (SCLK)
(5)
Therefore the maximum SCLK frequency is:
max f (SCLK)
+
12
tch 1 2 LSB
+
12
[In(8192)
Rt
Ci]
(6)
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