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參數資料
| 型號： | TLC320AC02IFNR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數： | 18/86頁 |
| 文件大小： | 471K |
| 代理商： | TLC320AC02IFNR |
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2–11
2.13.1
Slave and Codec Functional Sequence
The A counter counts according to the contents of the A register, and the A counter frequency is divided by
two to produce the FCLK. The device function in the slave or codec mode is the same as steps 1 through
3 of the B cycle description in the master mode but differs as follows:
1.
Same as master
2.
Same as master
3.
Same as master
4.
All internal clocks stop 1/2 FCLK before the end of count 0 in the B counter cycle.
5.
All internal clocks are restarted on the first rising edge of MCLK after the external FS input goes
low. This operation provides the synchronization necessary when using an external FS signal.
6.
The D-to-A conversion starts on the rising edge of the internally generated frame-sync interval
at the end of the 16-shift clock data transfer.
In the slave mode, the master controls the phase adjustments for itself and all slaves since all devices are
programmed in the same frame-sync interval. In the codec mode, the shift clock and frame sync are
externally generated and provide the timing for the ADC and DAC if the free-run function has not been
selected (see Subsection 2.15.4). In the codec mode, there is usually no need for phase adjustments;
however, any required phase adjustments must be made by adjusting the external frame-sync timing
(sampling time).
2.13.2
Slave Register Programming
When slave devices are used on power-up or reset, all slave frame-sync signals occur at the same time as
the master frame-sync signal and all slave devices are programmed during the master secondary frame-
sync interval with the same data as the master. The last register programmed must be the frame-sync delay
(FSD) register because the delay starts immediately on the rising edge of the seventeenth shift clock of that
frame- sync interval. After the FSD register programming is completed for the master and slave, the slave
primary frame interval is shifted in time (time slot allocated) according to the data contained in the slave FSD
registers. The master then generates frame-sync intervals for itself and each slave to synchronize the host
serial port for data transfers for itself and all slave devices.
The number of slaves is specified in the FSN register (register 8); therefore, the number of frame-sync
intervals generated by the master is equal to the number of slaves plus one (see Section 2.7). These master
frame-sync intervals are separated in time by the delay time specified by the FSD register (register 7). These
master-generated intervals are the only frame-sync interval signals applied to the host serial port to provide
the data-transfer time slot for the slave devices.
2.14 Terminal Functions
2.14.1
Frame-Sync Function
The frame-sync signal indicates that the device is ready to send and receive data for both master and slave
modes. The data transfer begins on the falling edge of the frame-sync signal.
2.14.1.1 Frame Sync (FS), Master Mode
The frame sync is generated internally. FS goes low on the rising edge of SCLK and remains low for the
16-bit data transfer. In addition to generating its own frame-sync interval, the master also outputs a frame
sync for each slave that is being used.
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