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參數(shù)資料
| 型號： | TLC3544CDW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 4-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, PLASTIC, SOIC-20 |
| 文件頁數(shù)： | 4/44頁 |
| 文件大小： | 1000K |
| 代理商： | TLC3544CDW |
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TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, AVDD = 5 V,
DVDD = 5 V, VREFP = 5 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued)
FS trigger
PARAMETERS
MIN
TYP
MAX
UNIT
td(8)
Delay time, delay from CS falling edge to FS rising edge, at 25-pF load
0.5
tc(1)
tsu(3)
Setup time, FS rising edge before SCLK falling edge, at 25-pF load
0.25
×tc(1)
0.5
×tc(1)+5
ns
tw(3)
Pulse width, FS high at 25-pF load
0.75
×tc(1)
tc(1)
1.25
×tc(1)
ns
t
Delay time, delay from FS rising edge to MSB of SDO valid
DVDD = 5 V
26
ns
td(9)
Delay time, delay from FS rising edge to MSB of SDO valid
(reaches 90% final level) at 10-pF load
DVDD = 2.7 V
30
ns
td(10) Delay time, delay from FS rising edge to next FS rising edge at 25-pF load
Required
sampling time +
conversion time
s
t
Delay time, delay from FS rising edge to INT rising edge at
DVDD = 5 V
0
6
ns
td(11)
Delay time, delay from FS rising edge to INT rising edge at
10-pF load
DVDD = 2.7 V
16
ns
Specified by design
ID15
OD1
OD0
ID1
Hi-Z
1
16
OD15
ID0
Don’t Care
ID15
OD15
OR
td(10)
tw(3)
td(8)
tsu(3)
td(9)
td(11)
Don’t Care
Hi-Z
VIH
VIL
VOH
CS
FS
SCLK
SDI
SDO
EOC
INT
NOTE A:
– – – – The dotted line means signal may or may not exist, depending on application. It must be ignored.
Normal sampling mode, FS initiates the conversion, CS can be tied to low. When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK, SDI)
are inactive and are ignored.
Parts with date code earlier than 13XXXXX have these discrepancies:
(Date code is a 7 digit code next to the TI where the first digit indicates the year and the second digit is the month of production. 13,
in this case, is 2001 and the month of March.)
SDO MSB (OD[15]) comes out from the falling edge of CS instead of FS rising edge in DSP mode (FS triggered).
Figure 3. Critical Timing for FS Trigger
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC3544CDW | 制造商:Texas Instruments 功能描述:14BIT ADC 4CH 5V 200KSPS 20SOIC 制造商:Texas Instruments 功能描述:14BIT ADC, 4CH, 5V, 200KSPS, 20SOIC |
| TLC3544CDWG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14B 5V 200KSPS 4-CH Unipolar ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLC3544CDWR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14-bit 5V 200KSPS 4-Channel Unipolar RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLC3544CDWRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14-bit 5V 200KSPS 4-Channel Unipolar RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLC3544CPW | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 14-bit 5V 200KSPS 4-Channel Unipolar RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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