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參數資料
| 型號： | TLC541IN |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 11-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP20 |
| 封裝： | ROHS COMPLIANT, PLASTIC, DIP-20 |
| 文件頁數： | 11/16頁 |
| 文件大小： | 296K |
| 代理商： | TLC541IN |
TLC540I, TLC541I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065B – OCTOBER 1983 – REVISED JUNE 2001
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
TLC540
TLC541
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
UNIT
Supply voltage, VCC
4.75
5
5.5
4.75
5
5.5
V
Positive reference voltage, Vref+ (see Note 2)
2.5
VCC VCC + 0.1
2.5
VCC VCC + 0.1
V
Negative reference voltage, Vref– (see Note 2)
– 0.1
0
2.5
– 0.1
0
2.5
V
Differential reference voltage, Vref+ – Vref– (see Note 2)
1
VCC VCC + 0.2
1
VCC VCC + 0.2
V
Analog input voltage (see Note 2)
0
VCC
0
VCC
V
High-level control input voltage, VIH
2
V
Low-level control input voltage, VIL
0.8
V
Setup time, address bits at data input before I/O CLOCK
↑,
tsu(A)
200
400
ns
Hold time, address bits after I/O CLOCK
↑,th(A)
0
ns
Setup time, CS low before clocking in first address bit, tsu(CS)
(see Note 3)
3
System
clock
cycles
CS high during conversion, twH(CS)
36
System
clock
cycles
I/O CLOCK frequency, fclock(I/O)
0
2.048
0
1.1
MHz
Pulse duration, SYSTEM CLOCK frequency, fclock(SYS)
fclock(I/O)
4
fclock(I/O)
2.1
MHz
Pulse duration, SYSTEM CLOCK high, twH(SYS)
110
210
MHz
Pulse duration, SYSTEM CLOCK low, twL(SYS)
100
190
MHz
Pulse duration, I/O clock high, twH(I/O)
200
404
ns
Pulse duration, I/O clock low, twL(I/O)
200
404
ns
System
fclock(SYS) ≤ 1048 kHz
30
Clock transition time
System
fclock(SYS) > 1048 kHz
20
ns
(see Note 4)
I/O
fclock(I/O) ≤ 525 kHz
100
ns
I/O
fclock(I/O) > 525 kHz
40
Operating free-air temperature, TA
TLC540I, TLC541I
– 40
85
– 40
85
°C
NOTES:
2. Analog input voltages greater than that applied to REF + convert as all 1s (11111111), while input voltages less than that applied to
REF– convert as all 0s (00000000). For proper operation, REF+ voltage must be at least 1 V higher than REF– voltage. Also, the
total unadjusted error may increase as this differential reference voltage falls below 4.75 V.
3. To minimize errors caused by noise at CS, the internal circuitry waits for three SYSTEM CLOCK cycles (or less) after a chip select
falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock in an address until
the minimum chip select setup time has elapsed.
4. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 2
s for remote data acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
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| TLC541INE4 | 功能描述:模數轉換器 - ADC 8Bit 40kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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