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參數資料
| 型號： | TLC542CDW |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 11-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, SOIC-20 |
| 文件頁數： | 8/12頁 |
| 文件大小： | 172K |
| 代理商： | TLC542CDW |
TLC542C, TLC542I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 4.75 to 5.5 V, f(clock I/O) = 1 MHZ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EL
Linearity error (see Note 5)
±0.5
LSB
EZS
Zero-scale error (see Note 6)
See Note 2
±0.5
LSB
EFS
Full-scale error (see Note 6)
See Note 2
±0.5
LSB
Total unadjusted error (see Note 7)
±0.5
LSB
Self-test output code
Input A11 address = 1011,
See Note 8
01111101
(126)
128
10000011
(130)
tc(1)
Conversion time
See operating sequence
20
s
tc(2)
Total access and conversion cycle time
See operating sequence
40
s
t(acq)
Channel acquisition time (sample cycle)
See operating sequence
16
s
t(v)
Time output data remains valid after I/O CLK
↓
See Figure 5
10
ns
td(IO-DATA)
Delay time, I/O CLK
↓ to data output valid
See Figure 5
400
ns
td(IO-EOC)
Delay time, 8th I/O CLK
↓ to EOC↓
See Figure 6
500
ns
td(EOC-DATA)
Delay time, EOC
↑ to data out (MSB)
See Figure 7
400
ns
tPZH, tPZL
Delay time, CS
↓ to data out (MSB)
See Figure 2
3.4
s
tPHZ, tPLZ
Delay time, CS
↑ to data out (MSB)
See Figure 2
150
ns
tr(EOC)
Rise time
See Figure 7
100
ns
tf(EOC)
Fall time
See Figure 6
100
ns
tr(bus)
Data bus rise time
See Figure 5
300
ns
tf(bus)
Data bus fall time
See Figure 5
300
ns
All typical values are at TA = 25°C.
NOTES:
2. Analog input voltages greater than that applied to REF + convert to all ones (11111111), while input voltages less than that applied
to REF – convert to all zeros (00000000). For proper operation, REF + must be at least 1 V higher than REF –. Also, the total
unadjusted error may increase as this differential reference voltage falls below 4.75 V.
5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
6. Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.
7. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors.
8. Both the input address and the output codes are expressed in positive logic. The A11 analog input signal is internally generated and
is used for test purposes.
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