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參數(shù)資料

型號(hào)：	TLC546IFNR
廠商：	TEXAS INSTRUMENTS INC
元件分類：	ADC
英文描述：	19-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC28
封裝：	PLASTIC, LCC-28
文件頁(yè)數(shù)：	3/15頁(yè)
文件大小：	202K
代理商：	TLC546IFNR

TLC545C, TLC545I, TLC546C, TLC546I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 19 INPUTS

SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

It is possible to connect SYSTEM CLOCK and I/O CLOCK together in special situations in which controlling circuitry

points must be minimized. In this case, the following special points must be considered in addition to the requirements

of the normal control sequence previously described.

The first two clocks are required for this device to recognize CS is at a valid low level when the common clock

signal is used as an I/O CLOCK. When CS is recognized by the device to be at a high level, the common clock

signal is used for the conversion clock also.

A low CS must be recognized before the I/O CLOCK can shift in an analog channel address. The device

recognizes a CS transition when the SYSTEM CLOCK terminal receives two positive edges and then a

negative edge. For this reason, after a CS negative edge, the first two clock cycles do not shift in the address.

Also, upon shifting in the address, CS must be raised after the eighth valid (10 total) I/O CLOCK. Otherwise,

additional common clock cycles are recognized as I/O CLOCKS and shift in an erroneous address.

For certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time.

This device accommodates these applications. Although the on-chip sample and hold begins sampling upon the

negative edge of the fourth valid I/O clock cycle, the hold function is not initiated until the negative edge of the eighth

valid I/O clock cycle. Thus, the control circuitry can leave the I/O clock signal in its high state during the eighth valid

I/O clock cycle, until the moment at which the analog signal must be converted. The TLC545/546 continues sampling

the analog input until the eighth valid falling edge of the I/O clock. The control circuitry or software must then

immediately lower the I/O clock signal to initiate the hold function at the desired point in time and to start conversion.

相關(guān)PDF資料	PDF描述
TLC546IFN	19-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC28
TLC545CN	19-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP28
TLC545IFNR	19-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC28
TLC545CNG4	19-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP28
TLC545ING4	19-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP28

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
TLC546IN	制造商:Rochester Electronics LLC 功能描述:- Bulk
TLC548	制造商:TI 制造商全稱:Texas Instruments 功能描述:8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
TLC548C	制造商:TI 制造商全稱:Texas Instruments 功能描述:8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
TLC548CD	功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8bit A/D w/Serial RoHS:否制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
TLC548CDG4	功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8bit A/D w/Serial RoHS:否制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32

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