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參數資料
| 型號： | TLC5615IDGKRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 12.5 us SETTLING TIME, 10-BIT DAC, PDSO8 |
| 封裝： | GREEN, PLASTIC, MSOP-8 |
| 文件頁數： | 21/21頁 |
| 文件大小： | 504K |
| 代理商： | TLC5615IDGKRG4 |
www.ti.com
BUFFER AMPLIFIER
EXTERNAL REFERENCE
LOGIC INTERFACE
SERIAL CLOCK AND UPDATE RATE
f
(SCLK)max +
1
t
w CH )
t
w CL
tp(CS) + 16
t
w CH )
t
w CL
) tw CS
SERIAL INTERFACE
10 Data Bits
x
12 Bits
MSB
LSB
2 Extra (Sub-LSB) Bits
x = don’t care
10 Data Bits
x
16 Bits
MSB
LSB
2 Extra (Sub-LSB) Bits
4 Upper Dummy Bits
x = don’t care
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
The output buffer has a rail-to-rail output with short circuit protection and can drive a 2k
load with a 100pF load
capacitance. Settling time is 12.5
s typical to within 0.5LSB of final value.
The reference voltage input is buffered, which makes the DAC input resistance not code dependent. Therefore,
the REFIN input resistance is 10M
and the REFIN input capacitance is typically 5pF independent of input
code. The reference voltage determines the DAC full-scale output.
The logic inputs function with either TTL or CMOS logic levels. However, using rail-to-rail CMOS logic achieves
the lowest power dissipation. The power requirement increases by approximately 2 times when using TTL logic
levels.
Figure 1 shows the TLC5615 timing. The maximum serial clock rate is:
or approximately 14MHz. The digital update rate is limited by the chip-select period, which is:
and is equal to 820ns which is a 1.21MHz update rate. However, the DAC settling time to 10 bits of 12.5
s limits
the update rate to 80kHz for full-scale input step transitions.
When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in most
significant bit first. The rising edge of the SLCK input shifts the data into the input register.
The rising edge of CS then transfers the data to the DAC register. When CS is high, input data cannot be
clocked into the input register. All CS transitions should occur when the SCLK input is low.
If the daisy chain (cascading) function (see daisy-chaining devices section) is not used, a 12-bit input data
sequence with the MSB first can be used as shown in Figure 10:
Figure 10. 12-Bit Input Data Sequence
or 16 bits of data can be transferred as shown in Figure 11 with the 4 upper dummy bits first.
Figure 11. 16-Bit Input Data Sequence
9
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TLC5615IDR | 功能描述:數模轉換器- DAC 10-Bit 12.5 us DAC Serial Input Lo-Pwr RoHS:否 制造商:Texas Instruments 轉換器數量:1 DAC 輸出端數量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| TLC5615IDRG4 | 功能描述:數模轉換器- DAC 10-Bit 12.5 us DAC Serial Input Lo-Pwr RoHS:否 制造商:Texas Instruments 轉換器數量:1 DAC 輸出端數量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| TLC5615IP | 功能描述:數模轉換器- DAC 10bit DAC RoHS:否 制造商:Texas Instruments 轉換器數量:1 DAC 輸出端數量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| TLC5615IPE4 | 功能描述:數模轉換器- DAC 10-Bit 12.5 us DAC Serial Input Lo-Pwr RoHS:否 制造商:Texas Instruments 轉換器數量:1 DAC 輸出端數量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| TLC5617 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS |
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