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參數(shù)資料
| 型號(hào)： | TLC5617ACD |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 12.5 us SETTLING TIME, 10-BIT DAC, PDSO8 |
| 文件頁(yè)數(shù)： | 10/21頁(yè) |
| 文件大小： | 307K |
| 代理商： | TLC5617ACD |
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TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS151B – JULY 1997 – REVISED MARCH 2000
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
linearity, offset, and gain error using single end supplies (continued)
For a DAC, linearity is measured between zero input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full-scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output voltage. For the
TLC5617, the zero-scale (offset) error is plus or minus 3 LSB maximum. The code is calculated from the
maximum specification for the negative offset.
power-supply bypassing and ground management
Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground
currents are well managed.
A 0.1-
F ceramic bypass capacitor should be connected between VDD and AGND and mounted with short leads
as close as possible to the device. Use of ferrite beads may further isolate the system analog and digital power
supplies.
Figures 26 shows the ground plane layout and bypassing technique.
0.1
F
Analog Ground Plane
1
2
3
4
8
7
6
5
Figure 26. Power-Supply Bypassing
saving power
Setting the DAC register to all 0s minimizes power consumption by the reference resistor array and the output
load when the system is not using the DAC.
ac considerations/analog feedthrough
Higher frequency analog input signals may couple to the output through internal stray capacitance. Analog
feedthrough is tested by holding CS high, setting the DAC code to all 0s, sweeping the frequency applied to
REFIN, and monitoring the DAC output.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLC5617AID | SERIAL INPUT LOADING, 12.5 us SETTLING TIME, 10-BIT DAC, PDSO8 |
| TLC5617CD | SERIAL INPUT LOADING, 12.5 us SETTLING TIME, 10-BIT DAC, PDSO8 |
| TLC5617IDR | SERIAL INPUT LOADING, 12.5 us SETTLING TIME, 10-BIT DAC, PDSO8 |
| TLC5617AIDR | SERIAL INPUT LOADING, 12.5 us SETTLING TIME, 10-BIT DAC, PDSO8 |
| TLC5617ACDR | SERIAL INPUT LOADING, 12.5 us SETTLING TIME, 10-BIT DAC, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC5617ACDR | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TLC5617AID | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TLC5617AIDR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TLC5617CD | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TLC5617CDR | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
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