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參數資料
| 型號： | TLC5620IN |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 10 us SETTLING TIME, 8-BIT DAC, PDIP14 |
| 封裝： | ROHS COMPLIANT, PLASTIC, DIP-14 |
| 文件頁數： | 10/17頁 |
| 文件大小： | 389K |
| 代理商： | TLC5620IN |
TLC5620C, TLC5620I
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagram
DAC
Power-On
Reset
Serial
Interface
× 2
Latch
DAC
× 2
Latch
DAC
× 2
LDAC
REFA
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
REFB
REFC
CLK
REFD
DATA
LOAD
DACA
DACB
DACC
DACD
8
2
3
4
5
7
6
8
13
12
11
10
9
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
CLK
7
I
Serial interface clock. The input digital data is shifted into the serial interface
register on the falling edge of the clock applied to the CLK terminal.
DACA
12
O
DAC A analog output
DACB
11
O
DAC B analog output
DACC
10
O
DAC C analog output
DACD
9
O
DAC D analog output
DATA
6
I
Serial interface digital data input. The digital code for the DAC is clocked into the
serial interface register serially. Each data bit is clocked into the register on the
falling edge of the clock signal.
GND
1
I
Ground return and reference terminal
LDAC
13
I
Load DAC. When the LDAC signal is high, no DAC output updates occur when
the input digital data is read into the serial interface. The DAC outputs are only
updated when LDAC is taken from high to low.
LOAD
8
I
Serial Interface load control. When LDAC is low, the falling edge of the LOAD
signal latches the digital data into the output latch and immediately produces the
analog voltage at the DAC output terminal.
REFA
2
I
Reference voltage input to DAC A. This voltage defines the output analog range.
REFB
3
I
Reference voltage input to DAC B. This voltage defines the output analog range.
REFC
4
I
Reference voltage input to DAC C. This voltage defines the output analog range.
REFD
5
I
Reference voltage input to DAC D. This voltage defines the output analog range.
VDD
14
I
Positive supply voltage
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