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參數資料
| 型號： | TLC5733IPM |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數： | 19/24頁 |
| 文件大?。?/td> | 347K |
| 代理商： | TLC5733IPM |
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104B – JULY 1995 – REVISED FEBRUARY 2001
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
A AVCC
62
I
Analog supply voltage of ADC A
AD8 – AD1
6 – 13
O
Data output of ADC A (LSB: AD1, MSB:AD8)
AIN
63
I
Analog input of ADC A
B AVCC
51
I
Analog supply voltage of ADC B
BD8 – BD1
17 – 24
O
Data output of ADC B (LSB: BD1, MSB:BD8)
BIN
50
I
Analog input of ADC B
C AVCC
30
I
Analog supply voltage of ADC C
CD8 – CD1
36 – 43
O
Data output of ADC C (LSB:CD1, MSB: CD8)
When MODE0 = L, MODE1 = L, CD8 outputs MSB flag of BD8 – BD5
When MODE0 = L, MODE1 = L, CD7 outputs MSB flag of BD8 – BD5
When MODE0 = L, MODE1 = H, CD8 outputs B channel flag of CD8 – BD1
CIN
31
I
Analog input of ADC C
CLK
56
I
Clock input. The clock frequency is normally 4
× the frequency subcarrier (fsc) for most video systems (see
Table 3). The nominal clock frequency is 14.31818 MHz for National Television System Committee (NTSC)
and 17.745 MHz for phase alteration line (PAL).
CLPEN
57
I
Clamp enable. When using an internal clamp pulse, CLPEN should be high. When using an external clamp
pulse, CLPEN should be low.
CLP OUT A
59
O
Clamping bias current of ADC A. A resistor-capacitor combination that sets the clamp timing.
CLP OUT B
54
O
Clamping bias current of ADC B. A resistor-capacitor combination that sets the clamp timing.
CLP OUT C
27
O
Clamping bias current of ADC C. A resistor-capacitor combination that sets the clamp timing.
CLPV A
60
O
Clamping level of ADC A. A capacitor is connected to CLPV A to set the clamp timing. The clamp level at
CLPV A is connected to an output code of 16 (0010000).
CLPV B
53
O
Clamping level of ADC B. A capacitor is connected to CLPV B to set the clamp timing. The clamp level at
CLPV B is connected to an output code of 128 (1000000).
CLPV C
28
O
Clamping level of ADC C. A capacitor is connected to CLPV C to set the clamp timing. The clamp level at
CLPV C is connected to an output code of 128 (1000000).
DGND
15
I
Digital ground
DVDD
26
I
Digital supply voltage
EXTCLP
55
I
External clamp pulse input. When EXTCLP and CLPEN are low, the internal clamp circuit cannot be used.
The external clamp pulse when used is active high.
GND A
64
I
Ground of ADC A
GND B
49
I
Ground of ADC B
GND C
32
I
Ground of ADC C
INIT
58
I
Output initialized. The output data is synchronous when INIT is taken high from low. INIT is a control terminal
that allows the external system to initialize the TLC5733A data conversion cycle. INIT is usually used at
power up or system reset.
MODE0
46
I
Output format mode selector 0. When MODE1 is low and MODE0 is low, output data format1 is selected.
When MODE1 is low and MODE0 is high, output data format2 is selected. When MODE1 is high and
MODE0 is low, output data format3 is selected. A high level on MODE1 and a high level on MODE0 is not
used.
MODE1
45
I
Output format mode selector 1. When MODE1 is low and MODE0 is low, output data format1 is selected.
When MODE1 is low and MODE0 is high, output data format2 is selected. When MODE1 is high and
MODE0 is low, output data format3 is selected. A high level on MODE1 and a high level on MODE0 is not
used.
NT/ PAL
3
I
NTSC/PAL control. NTSC/PAL should be low for NTSC and high for PAL.
OE A
2
I
Output enable A. OE A enables the output of ADC A.
OE B
47
I
Output enable B. OE B enables the output of ADC B.
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