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參數(shù)資料
| 型號： | TLC7528EFNR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | DUAL, PARALLEL, 8 BITS INPUT LOADING, 0.1 us SETTLING TIME, 8-BIT DAC, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁數(shù)： | 22/26頁 |
| 文件大小： | 616K |
| 代理商： | TLC7528EFNR |
TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS062C – JANUARY 1987 – REVISED SEPTEMBER 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range,
VrefA = VrefB = 10 V, VOA and VOB at 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VDD = 5 V
VDD = 15 V
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
Linearity error
±1/2
LSB
Settling time (to 1/2 LSB)
See Note 1
100
ns
Gain error
See Note 2
2.5
LSB
AC feedthrough
REFA to OUTA
See Note 3
–65
dB
AC feedthrough
REFB to OUTB
See Note 3
–65
dB
Temperature coefficient of gain
See Note 4
0.007
0.0035
%FSR/
°C
Propagation delay (from digital input to
90% of final analog output current)
See Note 5
80
ns
Channel-to-channel
REFA to OUTB
See Note 6
77
dB
isolation
REFB to OUTA
See Note 7
77
dB
Digital-to-analog glitch impulse area
Measured for code transition
from 00000000 to 11111111,
TA = 25°C
160
440
nV
s
Digital crosstalk
Measured for code transition
from 00000000 to 11111111,
TA = 25°C
30
60
nV
s
Harmonic distortion
Vi = 6 V, f = 1 kHz, TA = 25°C
–85
dB
NOTES:
1. OUTA, OUTB load = 100
, Cext = 13 pF; WR and CS at 0 V; DB0–DB7 at 0 V to VDD or VDD to 0 V.
2. Gain error is measured using an internal feedback resistor. Nominal full scale range (FSR) = Vref – 1 LSB.
3. Vref = 20 V peak-to-peak, 100-kHz sine wave; DAC data latches loaded with 00000000.
4. Temperature coefficient of gain measured from 0
°C to 25°C or from 25°C to 70°C.
5. VrefA = VrefB = 10 V; OUTA/OUTB load = 100 , Cext = 13 pF; WR and CS at 0 V; DB0–DB7 at 0 V to VDD or VDD to 0 V.
6. Both DAC latches loaded with 11111111; VrefA = 20 V peak-to-peak, 100-kHz sine wave; VrefB = 0; TA = 25°C.
7. Both DAC latches loaded with 11111111; VrefB = 20 V peak-to-peak, 100-kHz sine wave; VrefA = 0; TA = 25°C.
PRINCIPLES OF OPERATION
These devices contain two identical, 8-bit-multiplying D/A converters, DACA and DACB. Each DAC consists
of an inverted R-2R ladder, analog switches, and input data latches. Binary-weighted currents are switched
between DAC output and AGND, thus maintaining a constant current in each ladder leg independent of the
switch state. Most applications require only the addition of an external operational amplifier and voltage
reference. A simplified D/A circuit for DACA with all digital inputs low is shown in Figure 1.
Figure 2 shows the DACA equivalent circuit. A similar equivalent circuit can be drawn for DACB. Both DACs
share the analog ground terminal 1 (AGND). With all digital inputs high, the entire reference current flows to
OUTA. A small leakage current (IIkg) flows across internal junctions, and as with most semiconductor devices,
doubles every 10
°C. Co is due to the parallel combination of the NMOS switches and has a value that depends
on the number of switches connected to the output. The range of Co is 50 pF to 120 pF maximum. The equivalent
output resistance (ro) varies with the input code from 0.8R to 3R where R is the nominal value of the ladder
resistor in the R-2R network.
These devices interface to a microprocessor through the data bus, CS, WR, and DACA/DACB control signals.
When CS and WR are both low, the TLC7528 analog output, specified by the DACA/DACB control line,
responds to the activity on the DB0–DB7 data bus inputs. In this mode, the input latches are transparent and
input data directly affects the analog output. When either the CS signal or WR signal goes high, the data on the
DB0–DB7 inputs is latched until the CS and WR signals go low again. When CS is high, the data inputs are
disabled regardless of the state of the WR signal.
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