- 您現在的位置：買賣IC網 > PDF目錄98247 > TLV0832CDR (TEXAS INSTRUMENTS INC) 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 PDF資料下載
參數資料
| 型號： | TLV0832CDR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | GREEN, MS-012AA, SOIC-8 |
| 文件頁數： | 13/19頁 |
| 文件大小： | 489K |
| 代理商： | TLV0832CDR |
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3VOLT 8BIT ANALOGTODIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 SEPTEMBER 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
functional description
The TLV0831 and TLV0832 use a sample-data-comparator structure that converts differential analog inputs by
a successive-approximation routine. The input voltage to be converted is applied to an input terminal and is
compared to ground (single ended), or to an adjacent input (differential). The TLV0832 input terminals can be
assigned a positive (+) or negative () polarity. The TLV0831 contains only one differential input channel with
fixed polarity assignment; therefore it does not require addressing. The signal can be applied differentially,
between IN+ and IN, to the TLV0831 or can be applied to IN+ with IN grounded as a single ended input. When
the signal input applied to the assigned positive terminal is less than the signal on the negative terminal, the
converter output is all zeros.
Channel selection and input configuration are under software control using a serial-data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete
conversion process. A clock input is then received from the processor. An interval of one clock period is
automatically inserted to allow the selected multiplexed channel to settle. DO comes out of the high-impedance
state and provides a leading low for one clock period of multiplexer settling time. The SAR comparator compares
successive outputs from the resistive ladder with the incoming analog signal. The comparator output indicates
whether the analog input is greater than or less than the resistive-ladder output. As the conversion proceeds,
conversion data is simultaneously output from DO, with the most significant bit (MSB) first. After eight clock
periods, the conversion is complete. When CS goes high, all internal registers are cleared. At this time, the
output circuits go to the high-impedance state. If another conversion is desired, CS must make a high-to-low
transition followed by address information.
A TLV0832 input configuration is assigned during the multiplexer-addressing sequence. The multiplexer
address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single ended or differential. When the input is
differential, the polarity of the channel input is assigned. In addition to selecting the differential mode, the polarity
may also be selected. Either channel of the channel pair may be designated as the negative or positive input.
On each low-to-high transition of the clock input, the data on DI is clocked into the multiplexer-address shift
register. The first logic high on the input is the start bit. A 2-bit assignment word follows the start bit on the
TLV0832. On each successive low-to-high transition of the clock input, the start bit and assignment word are
shifted through the shift register. When the start bit is shifted into the start location of the multiplexer register,
the input channel is selected and conversion starts. The TLV0832 DI terminal to the multiplexer shift register
is disabled for the duration of the conversion.
The TLV0832 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. The DI and DO
terminals can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This
is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the
high-impedance state.
相關PDF資料 |
PDF描述 |
|---|---|
| TLV0831IDG4 | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| TLV0831IDRG4 | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| TLV0831IP | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP8 |
| TLV0832IDR | 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| TLV0831CDG4 | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TLV0832CDRG4 | 功能描述:模數轉換器 - ADC 8-Bit 44.7 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV0832CP | 功能描述:模數轉換器 - ADC 8bit A/D RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV0832CPE4 | 功能描述:模數轉換器 - ADC 8-Bit 44.7 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV0832I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL |
| TLV0832ID | 功能描述:模數轉換器 - ADC 8bit A/D RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
發布緊急采購，3分鐘左右您將得到回復。