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參數資料
| 型號： | TLV1549ID |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | GREEN, SOIC-8 |
| 文件頁數： | 17/19頁 |
| 文件大小： | 429K |
| 代理商： | TLV1549ID |
TLV1549C, TLV1549I, TLV1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL
SLAS071C – JANUARY 1993 – REVISED MARCH 1995
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VCC
3
3.3
3.6
V
Positive reference voltage, Vref+ (see Note 2)
VCC
V
Negative reference voltage, Vref– (see Note 2)
0
V
Differential reference voltage, Vref+ – Vref– (see Note 2)
2.5
VCC VCC+0.2
V
Analog input voltage (see Note 2)
0
VCC
V
High-level control input voltage, VIH
VCC = 3 V to 3.6 V
2
V
Low-level control input voltage, VIL
VCC = 3 V to 3.6 V
0.6
V
Clock frequency at I/O CLOCK (see Note 3)
0
2.1
MHz
Setup time, CS low before first I/O CLOCK
↑, tsu(CS) (see Note 4)
1.425
μs
Hold time, CS low after last I/O CLOCK
↓, th(CS)
0
ns
Pulse duration, I/O CLOCK high, twH(I/O)
190
ns
Pulse duration, I/O CLOCK low, twL(I/O)
190
ns
Transition time, I/O CLOCK, tt(I/O) (see Note 5 and Figure 5)
1
μs
Transition time, CS, tt(CS)
10
μs
TLV1549C
0
70
°C
Operating free-air temperature, TA
TLV1549I
–40
85
°C
TLV1549M
–55
125
°C
NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (1111111111), while input voltages less than that applied
to REF – convert as all zeros (0000000000). The TLV1549 is functional with reference voltages down to 1 V (Vref + – Vref–); however,
the electrical specifications are no longer applicable.
3. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (
≤ 2 V), at least one I/O CLOCK rising edge (≥ 2 V) must occur
within 9.5
μs.
4. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS
↓ before responding to the I/O CLOCK. Therefore, no attempt should be made to clock out the data until the minimum
CS setup time has elapsed.
5. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the device functions with input clock transition time as slow as 1
μs for remote data-acquisition
applications where the sensor and the A / D converter are placed several feet away from the controlling microprocessor.
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