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參數(shù)資料
| 型號： | TLV2544IPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | GREEN, PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 28/46頁 |
| 文件大小： | 1078K |
| 代理商： | TLV2544IPWRG4 |
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TLV2544, TLV2548
2.7V TO 5.5V, 12BIT, 200KSPS, 4/8CHANNEL, LOW POWER
SERIAL ANALOGTODIGITAL CONVERTERS WITH AUTOPOWERDOWN
SLAS198E FEBRUARY 1999 REVISED JUNE 2003
34
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DATA CODE INFORMATION
Parts with a date code earlier than 31xxxxx have the following discrepancies:
1.
Earlier devices react to FS input irrespective of the state of the CS signal
2.
The earlier silicon was designed with SDO prereleased half clock ahead. This means in the microcontroller
mode (FS=1) the SDO is changed on the rising edge of SCLK with a delay; and for DSP serial port (when
FS is active) the SDO is changed on the falling edge of SCLK with a delay. This helps the setup time for
processor input data, but may reduce the hold time for processor input data. It is recommended that a
100 pF capacitance be added to the SDO line of the ADC when interfacing with a slower processor that
requires longer input data hold time.
3.
For earlier silicon, the delay time is specified as:
MIN
NOM
MAX
UNIT
VCC = 4.5 V
SDO = 0 pF
16
Delay time, delay from SCLK falling edge (FS is active) or
VCC = 4.5 V
SDO = 100 pF
20
ns
Delay time, delay from SCLK falling edge (FS is active) or
SCLK rising edge (FS=1) to next SDO valid, td(SCLK-DOV).
VCC = 2.7 V
SDO = 0 pF
24
ns
SCLK rising edge (FS=1) to next SDO valid, td(SCLK-DOV).
VCC = 2.7 V
SDO = 100 pF
30
This is because the SDO is changed at the rising edge in the up mode with a delay. This is the hold time
required by the external digital host processor, therefore, a minimum value is specified. The newer silicon
has been revised with SDO changed at the falling edge in the up mode with a delay. Since at least 0.5 SCLK
exists as the hold time for the external host processor, the specified maximum value helps with the
calculation of the setup time requirement of the external digital host processor.
For an explanation of the DSP mode, reverse the rising/falling edges in item (2) above.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLV2544QD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 200 kSPS Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2544QDG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12B 200 kSPS ADC Ser. Out Lo Pwr RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2544QDR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12 Bit 200 kSPS Lo Pwr RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2544QDRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12B 200 kSPS ADC Ser. Out Lo Pwr RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2545CDGK | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 200 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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