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參數(shù)資料
| 型號： | TLV2545IDGKR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | GREEN, PLASTIC, MSOP-8 |
| 文件頁數(shù)： | 29/31頁 |
| 文件大小： | 778K |
| 代理商： | TLV2545IDGKR |
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TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E MARCH 2000 REVISED APRIL 2010
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
using CS as the FS input (continued)
SCLK and conversion speed
The input frequency of SCLK can range from 100 kHz to 20 MHz maximum. The ADC conversion uses a
separate internal oscillator with a minimum frequency of 4 MHz. The conversion cycle takes 14 internal oscillator
clocks to complete. This leads to a 3.5-μs conversion time. For a 20-MHz SCLK, the minimum total cycle time
is given by: 16x(1/20M)+14x(1/4M)+one SCLK = 4.35 μs. An additional SCLK is added to account for the
required CS and/or FS high time. These times specify the minimum cycle time for an active CS or FS signal.
If violated, the conversion terminates, invalidating the next data output cycle. Table 1 gives the maximum SCLK
frequency for a given supply voltage and operational mode.
control via pin 1 (CS, SPI interface)
All devices are compatible with this mode operation. A falling CS initiates the cycle (for TLV2541, the FS input
is tied to VDD). CS remains low for the entire cycle time (sample+convert+one SCLK) and can then be released.
NOTE:
IMPORTANT: A single SCLK is required whenever CS is high.
control via pin 1 (CS, DSP interface)
All devices are compatible with this mode of operation. The FS signal from a DSP is connected directly to the
CS input of the ADC. A falling edge on the CS input initiates the cycle. (For the TLV2541, the FS input can be
tied to VDD, although better performance can be achieved when using the FS input for control. Refer to the next
section.) The CS input should remain low for the entire cycle time (sample+convert+one SCLK) and can then
be released.
NOTE:
IMPORTANT: A single SCLK is required whenever CS is high. This should be of little consequence,
since SCLK is normally always present when interfacing with a DSP.
control via pin 1 and pin 7 (CS and FS or FS only, DSP interface)
Only the TLV2541 is compatible with this mode of operation. The CS input to the ADC can be controlled via a
general-purpose I/O pin from the DSP. The FS signal from the DSP is connected directly to the FS input of the
ADC. A falling edge on CS, if used, releases the MSB on the SDO output. When CS is not used, the rising FS
edge releases the MSB. The falling edge on the FS input while SCLK is high initiates the cycle. The CS and
FS inputs should remain low for the entire cycle time (sample+convert+one SCLK) and can then be released.
reference voltage
An external reference is applied via VREF. The voltage level applied to this pin establishes the upper limit of the
analog inputs to produce a full-scale reading. The value of VREF and the analog input should not exceed the
positive supply or be less than GND, consistent with the specified absolute maximum ratings. The digital output
is at full scale when the input signal is equal to or higher than VREF and at zero when the input signal is equal
to or lower than GND.
power down and power up
Autopower down is built into these devices in order to reduce power consumption. The actual power savings
depends on the inactive time between cycles and the power supply (loading) decoupling/storage capacitors.
Power-down takes effect immediately after the conversion is complete. This is fast enough to provide some
power savings between cycles with longer than 1 SCLK inactive time. The device power goes down to 5 μA
within 0.5 μs. To achieve the lowest power-down current (deep powerdown) of 1 μA requires 2-ms inactive time
between cycles. The power-down state is initiated at the end of conversion. These devices wake up immediately
at the next falling edge of CS or the rising edge of FS.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLV2545IDGKRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 200 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2545IDR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 200 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2545IDRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 200 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2548CDW | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12bit 200KSPS SAR RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2548CDWG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 200 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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