- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98251 > TLV2548CPWG4 (TEXAS INSTRUMENTS INC) 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 PDF資料下載
參數(shù)資料
| 型號： | TLV2548CPWG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 14/46頁 |
| 文件大小： | 1078K |
| 代理商： | TLV2548CPWG4 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
TLV2544, TLV2548
2.7V TO 5.5V, 12BIT, 200KSPS, 4/8CHANNEL, LOW POWER
SERIAL ANALOGTODIGITAL CONVERTERS WITH AUTOPOWERDOWN
SLAS198E FEBRUARY 1999 REVISED JUNE 2003
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (continued)
MIN
NOM
MAX
UNIT
Pulse width, SCLK low time, twL(SCLK) (See Figures 16 and 19)
0.4
0.6
SCLKs
Pulse width, SCLK high time, twH(SCLK) (See Figures 16 and 19)
0.4
0.6
SCLKs
Setup time, SDI valid before falling edge of SCLK (FS is active) or the rising edge of
SCLK (FS=1), tsu(DI-SCLK (See Figures 16 and 19)
25
ns
Hold time, SDI hold valid after falling edge of SCLK (FS is active) or the rising edge
of SCLK (FS=1), th(DI-SCLK) (See Figure 16)
5
ns
Delay time, delay from CS falling edge to SDO valid, td(CSL-DOV)
(See Figures 16 and 19)
25
ns
Delay time, delay from FS falling edge to SDO valid, td(FSL-DOV) (See Figure 16)
25
ns
Delay time, delay from SCLK falling edge (FS is
VCC = 4.5 V
SDO = 5 pF
0.5 SCLK
+ 9
Delay time, delay from SCLK falling edge (FS is
active) or SCLK rising edge (FS=1) to SDO valid,
td(SCLK-DOV). (See Figures 16 and 19).
VCC = 4.5 V
SDO = 25 pF
0.5 SCLK
+ 10
ns
td(SCLK-DOV). (See Figures 16 and 19).
For a date code later than xxx, see the date code
information item (3).
VCC = 2.7 V
SDO = 5 pF
0.5 SCLK
+ 18
ns
information item (3).
VCC = 2.7 V
SDO = 25 pF
0.5 SCLK
+ 19
Delay time, delay from 17th SCLK rising edge (FS is active) or the 16th falling edge
(FS=1) to EOC falling edge, td(SCLK-EOCL) (See Figures 16 and 19)
45
ns
Delay time, delay from 16th SCLK falling edge to INT falling edge (FS =1) or from
the 17th rising edge SCLK to INT falling edge (when FS active), td(SCLK-INTL)
(See Figure 19)
Min t(conv)
s
Delay time, delay from CS falling edge or FS rising edge to INT rising edge,
td(CSL-INTH) or td(FSH-INTH). See Figures 16, 17, 18 and 19)
1
50
ns
Delay time, delay from CS rising edge to CSTART falling edge, td(CSH-CSTARTL)
(See Figures 17 and 18)
100
ns
Delay time, delay from CSTART rising edge to EOC falling edge, td(CSTARTH-EOCL)
(See Figures 17 and 18)
1
50
ns
Pulse width, CSTART low time, twL(CSTART) (See Figures 17 and 18)
Min t(sample)
s
Delay time, delay from CSTART rising edge to CSTART falling edge,
td(CSTARTH-CSTARTL) (See Figure 18)
Max t(conv)
s
Delay time, delay from CSTART rising edge to INT falling edge, td(CSTARTH-INTL)
(See Figures 17 and 18)
Max t(conv)
s
Operating free-air temperature, TA
TLV2544C/TLV2548C
0
70
°C
Operating free-air temperature, TA
TLV2544I/TLV2548I
40
85
°C
相關PDF資料 |
PDF描述 |
|---|---|
| TLV2548IDW | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| TLV2544IDRG4 | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| TLV2544IPWRG4 | 4-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| TLV2548IPW | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| TLV2548IPWG4 | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TLV2548CPWR | 功能描述:模數(shù)轉換器 - ADC 12-Bit 200 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2548CPWRG4 | 功能描述:模數(shù)轉換器 - ADC 12-Bit 200 kSPS Serial Out RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2548EVM | 功能描述:EVALUATION MODULE FOR TLV2548 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉換器 (ADC) 系列:- 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| TLV2548IDW | 功能描述:模數(shù)轉換器 - ADC 12bit 200KSPS SAR RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2548IDWG4 | 功能描述:模數(shù)轉換器 - ADC 12bit 200KSPS SAR RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
發(fā)布緊急采購，3分鐘左右您將得到回復。