- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄98252 > TLV2553IPWR (TEXAS INSTRUMENTS INC) 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 PDF資料下載
參數(shù)資料
| 型號(hào)： | TLV2553IPWR |
| 廠(chǎng)商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, PLASTIC, TSSOP-20 |
| 文件頁(yè)數(shù)： | 15/29頁(yè) |
| 文件大?。?/td> | 603K |
| 代理商： | TLV2553IPWR |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)當(dāng)前第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
22
www.ti.com
PRINCIPLES OF OPERATION
Table 2. Command Set (CMR) and Configuration
SDI D[7:4]
Binary,
HEX
COMMAND
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
SELECT analog input channel 0
SELECT analog input channel 1
SELECT analog input channel 2
SELECT analog input channel 3
SELECT analog input channel 4
SELECT analog input channel 5
SELECT analog input channel 6
SELECT analog input channel 7
SELECT analog input channel 8
SELECT analog input channel 9
SELECT analog input channel 10
SELECT TEST,
Voltage = (VREF+ + VREF–)/2
SELECT TEST, Voltage = REFM
SELECT TEST, Voltage = REFP
SW POWERDOWN (analog + reference)
Reserved
CONFIGURATION
CFGR1
SDI
D[3:0]
D[3:2]
D1
D0
01: 8-bit output length
X0: 12-bit output length (see Note)
11: 16-bit output length
0: MSB out first
1: LSB out first
0: Unipolar binary
1: Bipolar 2s complement
NOTE: Select 12-bit output mode to achieve 200 KSPS
sampling rate.
data input—address/command bits
The four MSBs (D7–D4) of the input data register are the address or command. These can be used to address
one of the 11 input channels, address one of three reference-test voltages, or activate software power-down
mode. All address/command bits affect the current conversion, which is the conversion that immediately follows
the current I/O cycle. They also have access to CFGR1 except for command 1111b, which is reserved.
data output length
CFGR1 bits (D3 and D2) of the data register select the output data length. The data-length selection is valid
for the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the current
I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits can be
selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested.
With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current
conversion is output as a 12-bit serial data stream during the next I/O cycle. The current I/O cycle must be exactly
12 bits long for proper synchronization, even when this means corrupting the output data from a previous
conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle.
With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication
with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial
data stream during the next I/O cycle with the four LSBs always reset to 0 (pad bits). The current I/O cycle must
be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the
previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current
I/O cycle.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLV2553IDWRG4 | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| TLV2553IPWRG4 | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| TLV2553IDW | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| TLV2553IPWG4 | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| TLV2553IPW | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLV2553IPWRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 200 KSPS 11 Ch Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2553IPWRQ1 | 功能描述:12 Bit Analog to Digital Converter 11 Input 1 SAR 20-TSSOP 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 位數(shù):12 采樣率（每秒）:200k 輸入數(shù):11 輸入類(lèi)型:單端 數(shù)據(jù)接口:SPI 配置:MUX-S/H-ADC 無(wú)線(xiàn)電 - S/H:ADC:1:1 A/D 轉(zhuǎn)換器數(shù):1 架構(gòu):SAR 參考類(lèi)型:外部 電壓 - 電源，模擬:2.7 V ~ 5.5 V 電壓 - 電源，數(shù)字:2.7 V ~ 5.5 V 特性:- 工作溫度:-40°C ~ 85°C 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商器件封裝:20-TSSOP 標(biāo)準(zhǔn)包裝:1 |
| TLV2556EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 TLV2556 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類(lèi)型:ADC 工具用于評(píng)估:ADS130E08 接口類(lèi)型:SPI 工作電源電壓:- 6 V to + 6 V |
| TLV2556IDW | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 200 KSPS 11 Ch Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2556IDWG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 200 KSPS 11 Ch Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。