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參數資料
| 型號： | TLV2556IDWR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, PLASTIC, SOIC-20 |
| 文件頁數： | 26/37頁 |
| 文件大小： | 729K |
| 代理商： | TLV2556IDWR |
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TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
32
www.ti.com
PRINCIPLES OF OPERATION
chip-select input (CS)
CS enables and disables the device. During normal operation, CS should be low. Although the use of CS is not
necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data
transfer of several devices sharing the same bus.
When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing
its output data line to other devices that may share it. After an internally generated debounce time, I/O CLOCK
is inhibited, thus preventing any further change in the internal state.
When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce
time before the reset operation takes effect. After CS is debounced low, I/O CLOCK must remain inactive (low)
for a minimum time before a new I/O cycle can start.
CS can interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough
before the end of the current conversion cycle, the previous conversion result is saved in the internal output
buffer and shifted out during the next I/O cycle.
When CS is held low continuously for multiple cycles, the first data bit of the newly completed conversion occurs
on DATA OUT on the rising edge of EOC or falling edge of INT. Note that the first cycle in the series still requires
a transition of CS from high to low. When a new conversion is started after the last falling edge of I/O CLOCK,
EOC goes low and the serial output is forced low until EOC goes high again.
When CS is toggled between conversions, the first data bit occurs on DATA OUT on the falling edge of CS. On
each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next bit
in the serial conversion result until the required number of bits has been output.
power-down features
When command (D7–D4) 1110b is clocked into the input data register during the first four I/O CLOCK cycles,
the software power-down mode is selected. Software power down is activated on the falling edge of the fourth
I/O CLOCK pulse.
During software power down, all internal circuitry is put in a low-current standby mode. The internal reference
(if being used) is powered down. No conversion is performed. The internal output buffer keeps the previous
conversion cycle data results provided that all digital inputs are held above VCC – 0.5 V or below 0.5 V. The I/O
logic remains active so the current I/O cycle must be completed even when the power-down mode is selected.
Upon power-on reset and before the first I/O cycle, the converter normally begins in the power-down mode. The
device remains in the software power-down mode until a valid input address (other than command 1110b) is
clocked in. Upon completion of that I/O cycle, a normal conversion is performed with the results being shifted
out during the next I/O cycle. If using the internal reference, care must be taken to allow the reference to power
on completely before a valid conversion can be performed. It requires 1 ms to resume from a software power
down.
The ADC also has an auto power-down mode. This is transparent to users. The ADC goes into auto power down
within 1 I/O CLOCK cycle after the conversion is complete and resumes, with a small delay after an active CS
is sent to the ADC. This mode keeps built-in reference so resumption is fast enough to be used between cycles.
analog MUX
The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer
according to the input addresses shown in Table 2. The input multiplexer is a break-before-make type to reduce
input-to-input noise rejection resulting from channel switching. Sampling of the analog inputs starts on the falling
edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held on the
falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the multiplexer, then
sampled and converted in the same manner as the external analog inputs. The first conversion after the device
has returned from the power-down state may not read accurately due to internal device settling.
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| TLV2556IPWR | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TLV2556IDWRG4 | 功能描述:模數轉換器 - ADC 12B 200 KSPS 11Ch Lo Pwr Serial ADC RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2556IPW | 功能描述:模數轉換器 - ADC 12-Bit 200 KSPS 11 Ch Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2556IPW | 制造商:Texas Instruments 功能描述:12BIT ADC 200KSPS 2556 TSSOP20 制造商:Texas Instruments 功能描述:12BIT ADC, 200KSPS, 2556, TSSOP20 制造商:Texas Instruments 功能描述:12BIT ADC, 200KSPS, 2556, TSSOP20; Resolution (Bits):12bit; Sampling Rate:200kSPS; Supply Voltage Type:Single; Supply Voltage Min:2.7V; Supply Voltage Max:5.5V; Supply Current:3mA; Digital IC Case Style:TSSOP; No. of Pins:20; Input ;RoHS Compliant: Yes |
| TLV2556IPWG4 | 功能描述:模數轉換器 - ADC 12-Bit 200 KSPS 11 Ch Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2556IPWR | 功能描述:模數轉換器 - ADC 12-Bit 200 KSPS 11 Ch Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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